| Message ID | 1430273492-10784-2-git-send-email-sjg@chromium.org |
|---|---|
| State | Accepted |
| Delegated to: | Simon Glass |
| Headers | show |
On Wed, Apr 29, 2015 at 10:11 AM, Simon Glass <sjg@chromium.org> wrote: > Now that reset_cpu() functions correctly, use it instead of directly > accessing the port. > > Signed-off-by: Simon Glass <sjg@chromium.org> > --- > > Changes in v2: > - Correct call to reset_cpu() which was missing a parameter! > - Tidy up reset calls to do the correct reset type > > arch/x86/cpu/ivybridge/cpu.c | 5 ++--- > arch/x86/cpu/ivybridge/early_me.c | 13 +++---------- > arch/x86/cpu/ivybridge/sdram.c | 3 +-- > 3 files changed, 6 insertions(+), 15 deletions(-) > > diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c > index 37f3731..cce5923 100644 > --- a/arch/x86/cpu/ivybridge/cpu.c > +++ b/arch/x86/cpu/ivybridge/cpu.c > @@ -92,7 +92,7 @@ static int set_flex_ratio_to_tdp_nominal(void) > > /* Issue warm reset, will be "CPU only" due to soft reset data */ > outb(0x0, PORT_RESET); > - outb(0x6, PORT_RESET); > + outb(SYS_RST | RST_CPU, PORT_RESET); > cpu_hlt(); > > /* Not reached */ > @@ -286,8 +286,7 @@ int print_cpuinfo(void) > > /* System is not happy after keyboard reset... */ > debug("Issuing CF9 warm reset\n"); > - outb(0x6, 0xcf9); > - cpu_hlt(); > + reset_cpu(0); > } > > /* Early chipset init required before RAM init can work */ > diff --git a/arch/x86/cpu/ivybridge/early_me.c b/arch/x86/cpu/ivybridge/early_me.c > index 356bbb4..711470f 100644 > --- a/arch/x86/cpu/ivybridge/early_me.c > +++ b/arch/x86/cpu/ivybridge/early_me.c > @@ -117,7 +117,6 @@ static inline void set_global_reset(int enable) > > int intel_early_me_init_done(u8 status) > { > - u8 reset; > int count; > u32 mebase_l, mebase_h; > struct me_hfs hfs; > @@ -156,7 +155,6 @@ int intel_early_me_init_done(u8 status) > /* Check status after acknowledgement */ > intel_early_me_status(); > > - reset = 0; > switch (hfs.ack_data) { > case ME_HFS_ACK_CONTINUE: > /* Continue to boot */ > @@ -164,17 +162,17 @@ int intel_early_me_init_done(u8 status) > case ME_HFS_ACK_RESET: > /* Non-power cycle reset */ > set_global_reset(0); > - reset = 0x06; > + reset_cpu(0); > break; > case ME_HFS_ACK_PWR_CYCLE: > /* Power cycle reset */ > set_global_reset(0); > - reset = 0x0e; > + x86_full_reset(); > break; > case ME_HFS_ACK_GBL_RESET: > /* Global reset */ > set_global_reset(1); > - reset = 0x0e; > + x86_full_reset(); > break; > case ME_HFS_ACK_S3: > case ME_HFS_ACK_S4: > @@ -182,10 +180,5 @@ int intel_early_me_init_done(u8 status) > break; > } > > - /* Perform the requested reset */ > - if (reset) { > - outb(reset, 0xcf9); > - cpu_hlt(); > - } > return -1; > } > diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c > index 9a6da37..af907c5 100644 > --- a/arch/x86/cpu/ivybridge/sdram.c > +++ b/arch/x86/cpu/ivybridge/sdram.c > @@ -393,8 +393,7 @@ int sdram_initialise(struct pei_data *pei_data) > /* If MRC data is not found we cannot continue S3 resume. */ > if (pei_data->boot_mode == PEI_BOOT_RESUME && !pei_data->mrc_input) { > debug("Giving up in sdram_initialize: No MRC data\n"); > - outb(0x6, PORT_RESET); > - cpu_hlt(); > + reset_cpu(0); > } > > /* Pass console handler in pei_data */ > -- Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
On 28 April 2015 at 21:57, Bin Meng <bmeng.cn@gmail.com> wrote: > On Wed, Apr 29, 2015 at 10:11 AM, Simon Glass <sjg@chromium.org> wrote: >> Now that reset_cpu() functions correctly, use it instead of directly >> accessing the port. >> >> Signed-off-by: Simon Glass <sjg@chromium.org> >> --- >> >> Changes in v2: >> - Correct call to reset_cpu() which was missing a parameter! >> - Tidy up reset calls to do the correct reset type >> >> arch/x86/cpu/ivybridge/cpu.c | 5 ++--- >> arch/x86/cpu/ivybridge/early_me.c | 13 +++---------- >> arch/x86/cpu/ivybridge/sdram.c | 3 +-- >> 3 files changed, 6 insertions(+), 15 deletions(-) >> >> diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c >> index 37f3731..cce5923 100644 >> --- a/arch/x86/cpu/ivybridge/cpu.c >> +++ b/arch/x86/cpu/ivybridge/cpu.c >> @@ -92,7 +92,7 @@ static int set_flex_ratio_to_tdp_nominal(void) >> >> /* Issue warm reset, will be "CPU only" due to soft reset data */ >> outb(0x0, PORT_RESET); >> - outb(0x6, PORT_RESET); >> + outb(SYS_RST | RST_CPU, PORT_RESET); >> cpu_hlt(); >> >> /* Not reached */ >> @@ -286,8 +286,7 @@ int print_cpuinfo(void) >> >> /* System is not happy after keyboard reset... */ >> debug("Issuing CF9 warm reset\n"); >> - outb(0x6, 0xcf9); >> - cpu_hlt(); >> + reset_cpu(0); >> } >> >> /* Early chipset init required before RAM init can work */ >> diff --git a/arch/x86/cpu/ivybridge/early_me.c b/arch/x86/cpu/ivybridge/early_me.c >> index 356bbb4..711470f 100644 >> --- a/arch/x86/cpu/ivybridge/early_me.c >> +++ b/arch/x86/cpu/ivybridge/early_me.c >> @@ -117,7 +117,6 @@ static inline void set_global_reset(int enable) >> >> int intel_early_me_init_done(u8 status) >> { >> - u8 reset; >> int count; >> u32 mebase_l, mebase_h; >> struct me_hfs hfs; >> @@ -156,7 +155,6 @@ int intel_early_me_init_done(u8 status) >> /* Check status after acknowledgement */ >> intel_early_me_status(); >> >> - reset = 0; >> switch (hfs.ack_data) { >> case ME_HFS_ACK_CONTINUE: >> /* Continue to boot */ >> @@ -164,17 +162,17 @@ int intel_early_me_init_done(u8 status) >> case ME_HFS_ACK_RESET: >> /* Non-power cycle reset */ >> set_global_reset(0); >> - reset = 0x06; >> + reset_cpu(0); >> break; >> case ME_HFS_ACK_PWR_CYCLE: >> /* Power cycle reset */ >> set_global_reset(0); >> - reset = 0x0e; >> + x86_full_reset(); >> break; >> case ME_HFS_ACK_GBL_RESET: >> /* Global reset */ >> set_global_reset(1); >> - reset = 0x0e; >> + x86_full_reset(); >> break; >> case ME_HFS_ACK_S3: >> case ME_HFS_ACK_S4: >> @@ -182,10 +180,5 @@ int intel_early_me_init_done(u8 status) >> break; >> } >> >> - /* Perform the requested reset */ >> - if (reset) { >> - outb(reset, 0xcf9); >> - cpu_hlt(); >> - } >> return -1; >> } >> diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c >> index 9a6da37..af907c5 100644 >> --- a/arch/x86/cpu/ivybridge/sdram.c >> +++ b/arch/x86/cpu/ivybridge/sdram.c >> @@ -393,8 +393,7 @@ int sdram_initialise(struct pei_data *pei_data) >> /* If MRC data is not found we cannot continue S3 resume. */ >> if (pei_data->boot_mode == PEI_BOOT_RESUME && !pei_data->mrc_input) { >> debug("Giving up in sdram_initialize: No MRC data\n"); >> - outb(0x6, PORT_RESET); >> - cpu_hlt(); >> + reset_cpu(0); >> } >> >> /* Pass console handler in pei_data */ >> -- > > Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Applied to u-boot-x86.
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index 37f3731..cce5923 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -92,7 +92,7 @@ static int set_flex_ratio_to_tdp_nominal(void) /* Issue warm reset, will be "CPU only" due to soft reset data */ outb(0x0, PORT_RESET); - outb(0x6, PORT_RESET); + outb(SYS_RST | RST_CPU, PORT_RESET); cpu_hlt(); /* Not reached */ @@ -286,8 +286,7 @@ int print_cpuinfo(void) /* System is not happy after keyboard reset... */ debug("Issuing CF9 warm reset\n"); - outb(0x6, 0xcf9); - cpu_hlt(); + reset_cpu(0); } /* Early chipset init required before RAM init can work */ diff --git a/arch/x86/cpu/ivybridge/early_me.c b/arch/x86/cpu/ivybridge/early_me.c index 356bbb4..711470f 100644 --- a/arch/x86/cpu/ivybridge/early_me.c +++ b/arch/x86/cpu/ivybridge/early_me.c @@ -117,7 +117,6 @@ static inline void set_global_reset(int enable) int intel_early_me_init_done(u8 status) { - u8 reset; int count; u32 mebase_l, mebase_h; struct me_hfs hfs; @@ -156,7 +155,6 @@ int intel_early_me_init_done(u8 status) /* Check status after acknowledgement */ intel_early_me_status(); - reset = 0; switch (hfs.ack_data) { case ME_HFS_ACK_CONTINUE: /* Continue to boot */ @@ -164,17 +162,17 @@ int intel_early_me_init_done(u8 status) case ME_HFS_ACK_RESET: /* Non-power cycle reset */ set_global_reset(0); - reset = 0x06; + reset_cpu(0); break; case ME_HFS_ACK_PWR_CYCLE: /* Power cycle reset */ set_global_reset(0); - reset = 0x0e; + x86_full_reset(); break; case ME_HFS_ACK_GBL_RESET: /* Global reset */ set_global_reset(1); - reset = 0x0e; + x86_full_reset(); break; case ME_HFS_ACK_S3: case ME_HFS_ACK_S4: @@ -182,10 +180,5 @@ int intel_early_me_init_done(u8 status) break; } - /* Perform the requested reset */ - if (reset) { - outb(reset, 0xcf9); - cpu_hlt(); - } return -1; } diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index 9a6da37..af907c5 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -393,8 +393,7 @@ int sdram_initialise(struct pei_data *pei_data) /* If MRC data is not found we cannot continue S3 resume. */ if (pei_data->boot_mode == PEI_BOOT_RESUME && !pei_data->mrc_input) { debug("Giving up in sdram_initialize: No MRC data\n"); - outb(0x6, PORT_RESET); - cpu_hlt(); + reset_cpu(0); } /* Pass console handler in pei_data */
Now that reset_cpu() functions correctly, use it instead of directly accessing the port. Signed-off-by: Simon Glass <sjg@chromium.org> --- Changes in v2: - Correct call to reset_cpu() which was missing a parameter! - Tidy up reset calls to do the correct reset type arch/x86/cpu/ivybridge/cpu.c | 5 ++--- arch/x86/cpu/ivybridge/early_me.c | 13 +++---------- arch/x86/cpu/ivybridge/sdram.c | 3 +-- 3 files changed, 6 insertions(+), 15 deletions(-)