| Message ID | 1421730977-30077-11-git-send-email-sjg@chromium.org |
|---|---|
| State | Accepted |
| Delegated to: | Simon Glass |
| Headers | show |
On Tue, Jan 20, 2015 at 1:16 PM, Simon Glass <sjg@chromium.org> wrote: > Add a hook to ensure that this information is saved. > > Signed-off-by: Simon Glass <sjg@chromium.org> > --- > > Changes in v3: > - Add misc_init_r() call for link now that it is shared with chromebook_link > > Changes in v2: None > > arch/x86/cpu/coreboot/coreboot.c | 5 +++++ > include/configs/chromebook_link.h | 1 + > 2 files changed, 6 insertions(+) > > diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c > index 6d06d5a..4cdd0d4 100644 > --- a/arch/x86/cpu/coreboot/coreboot.c > +++ b/arch/x86/cpu/coreboot/coreboot.c > @@ -99,3 +99,8 @@ void panic_puts(const char *str) > while (*str) > NS16550_putc(port, *str++); > } > + > +int misc_init_r(void) > +{ > + return 0; > +} > diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h > index 7e6d239..6e8b9ef 100644 > --- a/include/configs/chromebook_link.h > +++ b/include/configs/chromebook_link.h > @@ -20,6 +20,7 @@ > > #define CONFIG_DCACHE_RAM_MRC_VAR_SIZE 0x4000 > #define CONFIG_BOARD_EARLY_INIT_F > +#define CONFIG_MISC_INIT_R > > #define CONFIG_NR_DRAM_BANKS 8 > #define CONFIG_X86_MRC_ADDR 0xfffa0000 > -- Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
On 19 January 2015 at 23:04, Bin Meng <bmeng.cn@gmail.com> wrote: > On Tue, Jan 20, 2015 at 1:16 PM, Simon Glass <sjg@chromium.org> wrote: >> Add a hook to ensure that this information is saved. >> >> Signed-off-by: Simon Glass <sjg@chromium.org> >> --- >> >> Changes in v3: >> - Add misc_init_r() call for link now that it is shared with chromebook_link >> >> Changes in v2: None >> >> arch/x86/cpu/coreboot/coreboot.c | 5 +++++ >> include/configs/chromebook_link.h | 1 + >> 2 files changed, 6 insertions(+) >> >> diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c >> index 6d06d5a..4cdd0d4 100644 >> --- a/arch/x86/cpu/coreboot/coreboot.c >> +++ b/arch/x86/cpu/coreboot/coreboot.c >> @@ -99,3 +99,8 @@ void panic_puts(const char *str) >> while (*str) >> NS16550_putc(port, *str++); >> } >> + >> +int misc_init_r(void) >> +{ >> + return 0; >> +} >> diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h >> index 7e6d239..6e8b9ef 100644 >> --- a/include/configs/chromebook_link.h >> +++ b/include/configs/chromebook_link.h >> @@ -20,6 +20,7 @@ >> >> #define CONFIG_DCACHE_RAM_MRC_VAR_SIZE 0x4000 >> #define CONFIG_BOARD_EARLY_INIT_F >> +#define CONFIG_MISC_INIT_R >> >> #define CONFIG_NR_DRAM_BANKS 8 >> #define CONFIG_X86_MRC_ADDR 0xfffa0000 >> -- > > Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Applied to u-boot-x86.
diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c index 6d06d5a..4cdd0d4 100644 --- a/arch/x86/cpu/coreboot/coreboot.c +++ b/arch/x86/cpu/coreboot/coreboot.c @@ -99,3 +99,8 @@ void panic_puts(const char *str) while (*str) NS16550_putc(port, *str++); } + +int misc_init_r(void) +{ + return 0; +} diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h index 7e6d239..6e8b9ef 100644 --- a/include/configs/chromebook_link.h +++ b/include/configs/chromebook_link.h @@ -20,6 +20,7 @@ #define CONFIG_DCACHE_RAM_MRC_VAR_SIZE 0x4000 #define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_MISC_INIT_R #define CONFIG_NR_DRAM_BANKS 8 #define CONFIG_X86_MRC_ADDR 0xfffa0000
Add a hook to ensure that this information is saved. Signed-off-by: Simon Glass <sjg@chromium.org> --- Changes in v3: - Add misc_init_r() call for link now that it is shared with chromebook_link Changes in v2: None arch/x86/cpu/coreboot/coreboot.c | 5 +++++ include/configs/chromebook_link.h | 1 + 2 files changed, 6 insertions(+)