| Message ID | 1384965766-28291-1-git-send-email-alban.bedel@avionic-design.de |
|---|---|
| State | Accepted |
| Delegated to: | Tom Warren |
| Headers | show |
On 11/20/2013 09:42 AM, Alban Bedel wrote: > The CPU complex reset masks are not matching with the datasheet for > the CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 registers. For both T20 > and T30 the register consist of groups of 4 bits, with one bit for > each CPU core. On T20 the 2 high bits of each group are always stubbed > as there is only 2 cores. This looks correct to me. Given this problem, it's surprising that reset_A9_cpu() was operating correctly, and that secondary CPUs were coming out of reset OK later. What testing has this had (which SoCs and boards)? But still, it matches the TRM and kernel code, so, Acked-by: Stephen Warren <swarren@nvidia.com>
On Thu, 21 Nov 2013 13:26:07 -0700 Stephen Warren <swarren@wwwdotorg.org> wrote: > On 11/20/2013 09:42 AM, Alban Bedel wrote: > > The CPU complex reset masks are not matching with the datasheet for > > the CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 registers. For both T20 > > and T30 the register consist of groups of 4 bits, with one bit for > > each CPU core. On T20 the 2 high bits of each group are always stubbed > > as there is only 2 cores. > > This looks correct to me. Given this problem, it's surprising that > reset_A9_cpu() was operating correctly, and that secondary CPUs were > coming out of reset OK later. What testing has this had (which SoCs and > boards)? I only tested it on T30 using our Tamonten NG board. Alban
On 11/25/2013 03:54 AM, Alban Bedel wrote: > On Thu, 21 Nov 2013 13:26:07 -0700 > Stephen Warren <swarren@wwwdotorg.org> wrote: > >> On 11/20/2013 09:42 AM, Alban Bedel wrote: >>> The CPU complex reset masks are not matching with the datasheet for >>> the CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 registers. For both T20 >>> and T30 the register consist of groups of 4 bits, with one bit for >>> each CPU core. On T20 the 2 high bits of each group are always stubbed >>> as there is only 2 cores. >> >> This looks correct to me. Given this problem, it's surprising that >> reset_A9_cpu() was operating correctly, and that secondary CPUs were >> coming out of reset OK later. What testing has this had (which SoCs and >> boards)? > > I only tested it on T30 using our Tamonten NG board. OK, I tested on all Tegra SoCs, and everything (including a CPU hotplug test in a kernel once booted with the new U-Boot) still works, so, Tested-by: Stephen Warren <swrren@nvidia.com>
diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h index c3174bd..e7d0fd4 100644 --- a/arch/arm/include/asm/arch-tegra/clock.h +++ b/arch/arm/include/asm/arch-tegra/clock.h @@ -113,9 +113,9 @@ void reset_set_enable(enum periph_id periph_id, int enable); enum crc_reset_id { /* Things we can hold in reset for each CPU */ crc_rst_cpu = 1, - crc_rst_de = 1 << 2, /* What is de? */ - crc_rst_watchdog = 1 << 3, - crc_rst_debug = 1 << 4, + crc_rst_de = 1 << 4, /* What is de? */ + crc_rst_watchdog = 1 << 8, + crc_rst_debug = 1 << 12, }; /**
The CPU complex reset masks are not matching with the datasheet for the CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 registers. For both T20 and T30 the register consist of groups of 4 bits, with one bit for each CPU core. On T20 the 2 high bits of each group are always stubbed as there is only 2 cores. Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de> --- arch/arm/include/asm/arch-tegra/clock.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)