| Message ID | 1319162491-2293-3-git-send-email-festevam@gmail.com |
|---|---|
| State | Accepted |
| Commit | 199222fcd280dc7abde193e0ba4a649c5cc32fbb |
| Delegated to: | Stefano Babic |
| Headers | show |
On 10/21/2011 04:01 AM, Fabio Estevam wrote: > On qong board some of the USBH2 pins are set via GPR register, so don need to setup > the IOMUX for each pin individually. > > Other than that, these pins should not be configured as primary function because the primary > function selects SSI functionality. > > Let GPR register do the work and remove the unneeded IOMUX setup. > > Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> > --- > Hi Fabio, > Stefano, > > I don't have access to the qong board to test this, but I believe this is the right thing to do here. I have not written this code and I do not know the history, but reading the manual I agree with you. The setup of the iomux is ininfluent, because the pins are already set in "Hardware mode 2" in the GPR register (GPR[11]). > > board/davedenx/qong/qong.c | 6 ------ > 1 files changed, 0 insertions(+), 6 deletions(-) > > diff --git a/board/davedenx/qong/qong.c b/board/davedenx/qong/qong.c > index de32fb5..70af593 100644 > --- a/board/davedenx/qong/qong.c > +++ b/board/davedenx/qong/qong.c > @@ -120,12 +120,6 @@ int board_early_init_f(void) > mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_STP, MUX_CTL_FUNC)); > mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA0, MUX_CTL_FUNC)); > mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA1, MUX_CTL_FUNC)); > - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_STXD3, MUX_CTL_FUNC)); > - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SRXD3, MUX_CTL_FUNC)); > - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SCK3, MUX_CTL_FUNC)); > - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SFS3, MUX_CTL_FUNC)); > - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_STXD6, MUX_CTL_FUNC)); > - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SRXD6, MUX_CTL_FUNC)); > > #define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ > PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) Acked-by: Stefano Babic <sbabic@denx.de> Best regards, Stefano Babic
diff --git a/board/davedenx/qong/qong.c b/board/davedenx/qong/qong.c index de32fb5..70af593 100644 --- a/board/davedenx/qong/qong.c +++ b/board/davedenx/qong/qong.c @@ -120,12 +120,6 @@ int board_early_init_f(void) mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_STP, MUX_CTL_FUNC)); mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA0, MUX_CTL_FUNC)); mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA1, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_STXD3, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SRXD3, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SCK3, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SFS3, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_STXD6, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SRXD6, MUX_CTL_FUNC)); #define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
On qong board some of the USBH2 pins are set via GPR register, so don need to setup the IOMUX for each pin individually. Other than that, these pins should not be configured as primary function because the primary function selects SSI functionality. Let GPR register do the work and remove the unneeded IOMUX setup. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> --- Stefano, I don't have access to the qong board to test this, but I believe this is the right thing to do here. board/davedenx/qong/qong.c | 6 ------ 1 files changed, 0 insertions(+), 6 deletions(-)