From patchwork Fri Oct 21 02:01:31 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Estevam X-Patchwork-Id: 120923 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id E18DDB7010 for ; Fri, 21 Oct 2011 13:02:27 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id CAF8D284F8; Fri, 21 Oct 2011 04:02:09 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id faOswpbETMLI; Fri, 21 Oct 2011 04:02:09 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B1515284FE; Fri, 21 Oct 2011 04:02:00 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 85F4D28466 for ; Fri, 21 Oct 2011 04:01:56 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 3RKPIweSI5VN for ; Fri, 21 Oct 2011 04:01:49 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-gy0-f172.google.com (mail-gy0-f172.google.com [209.85.160.172]) by theia.denx.de (Postfix) with ESMTPS id 5A93E28C95 for ; Fri, 21 Oct 2011 04:01:45 +0200 (CEST) Received: by gyh20 with SMTP id 20so3332611gyh.3 for ; Thu, 20 Oct 2011 19:01:43 -0700 (PDT) Received: by 10.236.190.200 with SMTP id e48mr18875345yhn.59.1319162503878; Thu, 20 Oct 2011 19:01:43 -0700 (PDT) Received: from localhost.localdomain ([187.106.42.141]) by mx.google.com with ESMTPS id f24sm16974801yhk.5.2011.10.20.19.01.41 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 20 Oct 2011 19:01:43 -0700 (PDT) From: Fabio Estevam To: u-boot@lists.denx.de Date: Fri, 21 Oct 2011 00:01:31 -0200 Message-Id: <1319162491-2293-3-git-send-email-festevam@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1319162491-2293-1-git-send-email-festevam@gmail.com> References: <1319162491-2293-1-git-send-email-festevam@gmail.com> Cc: Fabio Estevam Subject: [U-Boot] [PATCH 3/3] qong: remove unneeded IOMUX settings X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de On qong board some of the USBH2 pins are set via GPR register, so don need to setup the IOMUX for each pin individually. Other than that, these pins should not be configured as primary function because the primary function selects SSI functionality. Let GPR register do the work and remove the unneeded IOMUX setup. Signed-off-by: Fabio Estevam Acked-by: Stefano Babic --- Stefano, I don't have access to the qong board to test this, but I believe this is the right thing to do here. board/davedenx/qong/qong.c | 6 ------ 1 files changed, 0 insertions(+), 6 deletions(-) diff --git a/board/davedenx/qong/qong.c b/board/davedenx/qong/qong.c index de32fb5..70af593 100644 --- a/board/davedenx/qong/qong.c +++ b/board/davedenx/qong/qong.c @@ -120,12 +120,6 @@ int board_early_init_f(void) mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_STP, MUX_CTL_FUNC)); mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA0, MUX_CTL_FUNC)); mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA1, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_STXD3, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SRXD3, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SCK3, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SFS3, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_STXD6, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SRXD6, MUX_CTL_FUNC)); #define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)