Show patches with: Submitter = Shengyu Qu       |    Archived = No       |   21 patches
Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[v1,2/2] board: visionfive2: Fixup memory size passed to kernel Fix memory size problem on Visionfive 2 - - - 1 --- 2023-09-16 Shengyu Qu Andes Accepted
[v1,1/2] configs: visionfive2: Enable CONFIG_OF_BOARD_SETUP Fix memory size problem on Visionfive 2 - - - 1 --- 2023-09-16 Shengyu Qu Andes Accepted
[v6,4/4] configs: starfive: Disable SYS_MALLOC_CLEAR_ON_INIT by default arch: riscv: jh7110: Correctly zero L2 LIM - - 1 - --- 2023-08-24 Shengyu Qu Andes Accepted
[v6,3/4] riscv: cpu: jh7110: Imply SPL_SYS_MALLOC_CLEAR_ON_INIT arch: riscv: jh7110: Correctly zero L2 LIM - - 1 - --- 2023-08-24 Shengyu Qu Andes Accepted
[v6,2/4] dlmalloc: Add support for SPL_SYS_MALLOC_CLEAR_ON_INIT arch: riscv: jh7110: Correctly zero L2 LIM - - 1 - --- 2023-08-24 Shengyu Qu Andes Accepted
[v6,1/4] Kconfig: Add SPL_SYS_MALLOC_CLEAR_ON_INIT arch: riscv: jh7110: Correctly zero L2 LIM - - 1 - --- 2023-08-24 Shengyu Qu Andes Accepted
[v5,3/3] riscv: cpu: jh7110: Imply SPL_SYS_MALLOC_CLEAR_ON_INIT arch: riscv: jh7110: Correctly zero L2 LIM - - - - --- 2023-08-23 Shengyu Qu Andes Changes Requested
[v5,2/3] dlmalloc: Add support for SPL_SYS_MALLOC_CLEAR_ON_INIT arch: riscv: jh7110: Correctly zero L2 LIM - - 1 - --- 2023-08-23 Shengyu Qu Andes Changes Requested
[v5,1/3] Kconfig: Add SPL_SYS_MALLOC_CLEAR_ON_INIT arch: riscv: jh7110: Correctly zero L2 LIM - - - - --- 2023-08-23 Shengyu Qu Andes Changes Requested
[v1,2/2] doc: board: starfive: Add more info about supported driver Enable PCIE and USB by default on Visionfive 2 - - - 2 --- 2023-08-22 Shengyu Qu Andes Accepted
[v1,1/2] configs: starfive: Enable PCIE auto enum and NVME/USB stuff for Starfive Visionfive 2 Enable PCIE and USB by default on Visionfive 2 - - - 2 --- 2023-08-22 Shengyu Qu Andes Accepted
[v4,3/3] riscv: cpu: jh7110: Select SPL_ZERO_MEM_BEFORE_USE arch: riscv: jh7110: Correctly zero L2 LIM - - 1 - --- 2023-08-09 Shengyu Qu Andes Accepted
[v4,2/3] riscv: Add SPL_ZERO_MEM_BEFORE_USE implementation arch: riscv: jh7110: Correctly zero L2 LIM - - 1 - --- 2023-08-09 Shengyu Qu Andes Accepted
[v4,1/3] riscv: Kconfig: Add SPL_ZERO_MEM_BEFORE_USE arch: riscv: jh7110: Correctly zero L2 LIM - - 1 - --- 2023-08-09 Shengyu Qu Andes Accepted
[v1] configs: starfive: Enable environment in SPI flash support [v1] configs: starfive: Enable environment in SPI flash support - - 1 - --- 2023-08-08 Shengyu Qu Andes Accepted
[v3,3/3] riscv: cpu: jh7110: Select SPL_ZERO_MEM_BEFORE_USE arch: riscv: jh7110: Correctly zero L2 LIM - - 1 - --- 2023-08-08 Shengyu Qu Andes Superseded
[v3,2/3] riscv: Add SPL_ZERO_MEM_BEFORE_USE implementation arch: riscv: jh7110: Correctly zero L2 LIM - - - - --- 2023-08-08 Shengyu Qu Andes Superseded
[v3,1/3] riscv: Kconfig: Add SPL_ZERO_MEM_BEFORE_USE arch: riscv: jh7110: Correctly zero L2 LIM - - 1 - --- 2023-08-08 Shengyu Qu Andes Superseded
[v2,3/3] riscv: cpu: jh7110: Select SPL_ZERO_MEM_BEFORE_USE arch: riscv: jh7110: Correctly zero L2 LIM - - - - --- 2023-08-07 Shengyu Qu Andes Superseded
[v2,2/3] riscv: Add ZERO_MEM_BEFORE_USE implementation arch: riscv: jh7110: Correctly zero L2 LIM - - - - --- 2023-08-07 Shengyu Qu Andes Superseded
[v2,1/3] riscv: Kconfig: Add SPL_ZERO_MEM_BEFORE_USE arch: riscv: jh7110: Correctly zero L2 LIM - - - - --- 2023-08-07 Shengyu Qu Andes Superseded