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[v5,3/3] riscv: cpu: jh7110: Imply SPL_SYS_MALLOC_CLEAR_ON_INIT

Message ID TY3P286MB26114433D37E24F0CFFB95D1981CA@TY3P286MB2611.JPNP286.PROD.OUTLOOK.COM
State Changes Requested
Delegated to: Andes
Headers show
Series arch: riscv: jh7110: Correctly zero L2 LIM | expand

Commit Message

Shengyu Qu Aug. 23, 2023, 3:21 a.m. UTC 
Starfive JH7110 needs to clear L2 LIM to zero before use or ECC error
would be triggered. Currently, we use DDR ram for SPL malloc arena on
Visionfive 2 board in defconfig, but it's also possible to use L2 LIM as
SPL malloc arena. To avoid triggering ECC error in this scenario, we
imply SPL_SYS_MALLOC_CLEAR_ON_INIT as default.

Signed-off-by: Bo Gan <ganboing@gmail.com>
Signed-off-by: Shengyu Qu <wiagn233@outlook.com>
---
 arch/riscv/cpu/jh7110/Kconfig | 1 +
 1 file changed, 1 insertion(+)
diff mbox series

Patch

diff --git a/arch/riscv/cpu/jh7110/Kconfig b/arch/riscv/cpu/jh7110/Kconfig
index 8469ee7de5..e5549a01b8 100644
--- a/arch/riscv/cpu/jh7110/Kconfig
+++ b/arch/riscv/cpu/jh7110/Kconfig
@@ -28,3 +28,4 @@  config STARFIVE_JH7110
 	imply SPL_LOAD_FIT
 	imply SPL_OPENSBI
 	imply SPL_RISCV_ACLINT
+	imply SPL_SYS_MALLOC_CLEAR_ON_INIT