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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[RESEND,1/7] riscv: dts: Introduce SPL_LOAD_FIT_CONFIG symbol riscv: spl: OpenSBI OS boot mode - - - - --- 2023-10-06 Randolph Andes Superseded
[1/1] configs: sifive: enable poweroff command on Unmatched [1/1] configs: sifive: enable poweroff command on Unmatched - - 2 - --- 2023-10-01 Heinrich Schuchardt Andes Accepted
[v2] riscv: andesv5: Prefer using the generic RISC-V timer driver in S-mode [v2] riscv: andesv5: Prefer using the generic RISC-V timer driver in S-mode - - 1 - --- 2023-09-29 Yu Chien Peter Lin Andes Accepted
riscv: andesv5: Prefer using the generic RISC-V timer driver in S-mode riscv: andesv5: Prefer using the generic RISC-V timer driver in S-mode - - 1 - --- 2023-09-27 Yu Chien Peter Lin Andes Superseded
[1/1] riscv: remove dram_init_banksize() [1/1] riscv: remove dram_init_banksize() - - 1 - --- 2023-09-26 Heinrich Schuchardt Andes Accepted
[7/7] riscv: spl: andes: Move the DTB in front of kernel riscv: spl: OpenSBI OS boot mode - - - - --- 2023-09-25 Randolph Andes Superseded
[6/7] andes: config: add riscv falcon mode for ae350 platform riscv: spl: OpenSBI OS boot mode - - - - --- 2023-09-25 Randolph Andes Superseded
[5/7] spl: riscv: add os type for next booting stage riscv: spl: OpenSBI OS boot mode - - - - --- 2023-09-25 Randolph Andes Superseded
[4/7] riscv: dts: introduce SPL_LOAD_FIT_OPENSBI_OS_BOOT symbol riscv: spl: OpenSBI OS boot mode - - - - --- 2023-09-25 Randolph Andes Superseded
[3/7] spl: riscv: opensbi: change the default os_type as varible riscv: spl: OpenSBI OS boot mode - - - - --- 2023-09-25 Randolph Andes Superseded
[2/7] riscv: dts: add binman_linux.dtsi for opensbi os boot mode riscv: spl: OpenSBI OS boot mode - - - - --- 2023-09-25 Randolph Andes Superseded
[1/7] riscv: dts: Introduce SPL_LOAD_FIT_CONFIG symbol riscv: spl: OpenSBI OS boot mode - - - - --- 2023-09-25 Randolph Andes Superseded
[V3,2/2] configs: andes: rearrange SPL mode memory layout andes: rearrange defconfig and dts - - 1 - --- 2023-09-25 Randolph Andes Accepted
[V3,1/2] configs: andes: add vender prefix for target name andes: rearrange defconfig and dts - - 1 - --- 2023-09-25 Randolph Andes Accepted
[1/1] riscv: enable CONFIG_DEBUG_UART by default [1/1] riscv: enable CONFIG_DEBUG_UART by default - - 2 - --- 2023-09-22 Heinrich Schuchardt Andes Accepted
[1/1] cmd/exception: test RISC-V 16 bit aligned instruction [1/1] cmd/exception: test RISC-V 16 bit aligned instruction - - 1 - --- 2023-09-21 Heinrich Schuchardt Andes Accepted
[1/1] cmd/exception: support RISC-V compressed instruction [1/1] cmd/exception: support RISC-V compressed instruction - - 1 - --- 2023-09-21 Heinrich Schuchardt Andes Accepted
timer: starfive: Add Starfive timer support timer: starfive: Add Starfive timer support - - 2 - --- 2023-09-19 Kuan Lim Lee Andes Accepted
[1/1] starfive: visionfive2: add mmc0 and nvme boot targets [1/1] starfive: visionfive2: add mmc0 and nvme boot targets - - 1 - --- 2023-09-18 Milan P. Stanić Andes Accepted
[v3,2/2] riscv: dts: starfive: generate u-boot-spl.bin.normal.out riscv: starfive: generate u-boot-spl.bin.normal.out - - - 1 --- 2023-09-17 Heinrich Schuchardt Andes Accepted
[v3,1/2] tools: mkimage: Add StarFive SPL image support riscv: starfive: generate u-boot-spl.bin.normal.out - - - 2 --- 2023-09-17 Heinrich Schuchardt Andes Accepted
[v1,2/2] board: visionfive2: Fixup memory size passed to kernel Fix memory size problem on Visionfive 2 - - - 1 --- 2023-09-16 Shengyu Qu Andes Accepted
[v1,1/2] configs: visionfive2: Enable CONFIG_OF_BOARD_SETUP Fix memory size problem on Visionfive 2 - - - 1 --- 2023-09-16 Shengyu Qu Andes Accepted
[v2] riscv: enable multi-range memory layout [v2] riscv: enable multi-range memory layout - - - - --- 2023-09-14 Wu, Fei Andes New
[RFC,2/2] configs: visionfive2: Enable MISC_INIT_R board: visionfive2: Select fdtfile based on revision - - - 1 --- 2023-09-11 Jami Kettunen Andes RFC
[RFC,1/2] board: visionfive2: Select fdtfile based on revision board: visionfive2: Select fdtfile based on revision - - - 1 --- 2023-09-11 Jami Kettunen Andes RFC
[2/2] sifive: ccache: add clear LIM area [1/2] cache: sifive: clear out the error irqs on init - - - - --- 2023-09-08 Ben Dooks Andes Rejected
[1/2] cache: sifive: clear out the error irqs on init [1/2] cache: sifive: clear out the error irqs on init - - - - --- 2023-09-08 Ben Dooks Andes Rejected
[1/1] configs: NVMe/USB target boot devices on VisionFive 2 [1/1] configs: NVMe/USB target boot devices on VisionFive 2 - - 1 - --- 2023-09-07 Heinrich Schuchardt Andes Accepted
[1/1] riscv: set fdtfile on VisionFive 2 [1/1] riscv: set fdtfile on VisionFive 2 - - 1 1 --- 2023-09-07 Heinrich Schuchardt Andes Accepted
[v2,2/2] riscv: dts: starfive: generate u-boot-spl.bin.normal.out riscv: starfive: generate u-boot-spl.bin.normal.out - - - 2 --- 2023-09-06 Heinrich Schuchardt Andes Superseded
[v2,1/2] tools: mkimage: Add StarFive SPL image support riscv: starfive: generate u-boot-spl.bin.normal.out - - - 2 --- 2023-09-06 Heinrich Schuchardt Andes Superseded
[v3,3/3] timer: riscv_aclint_timer: add timer_get_boot_us for BOOTSTAGE bootstage support for risc-v - - 1 - --- 2023-09-06 Chanho Park Andes Accepted
[v3,2/3] riscv: timer: add timer_get_boot_us for BOOTSTAGE bootstage support for risc-v - - 1 - --- 2023-09-06 Chanho Park Andes Accepted
[v3,1/3] riscv: bootstage: correct bootstage_report guard bootstage support for risc-v - - 1 - --- 2023-09-06 Chanho Park Andes Accepted
[[PATCH,v2] ] riscv: add backtrace support [[PATCH,v2] ] riscv: add backtrace support - - - 1 --- 2023-09-05 Ben Dooks Andes Accepted
riscv: enable multi-range memory layout riscv: enable multi-range memory layout - - - - --- 2023-09-05 Wu, Fei Andes Superseded
[v2,2/2] risc-v: implement DBCN based debug console risc-v: implement DBCN based debug console - - 1 - --- 2023-09-04 Heinrich Schuchardt Andes Accepted
[v2,1/2] risc-v: implement DBCN write byte risc-v: implement DBCN based debug console - - 1 - --- 2023-09-04 Heinrich Schuchardt Andes Accepted
spl: add __noreturn attribute to spl_invoke_opensbi function spl: add __noreturn attribute to spl_invoke_opensbi function - - 1 - --- 2023-08-29 Chanho Park Andes Accepted
[v2,3/3] timer: riscv_aclint_timer: add timer_get_boot_us for BOOTSTAGE bootstage support for risc-v - - - - --- 2023-08-28 Chanho Park Andes Changes Requested
[v2,2/3] riscv: timer: add timer_get_boot_us for BOOTSTAGE bootstage support for risc-v - - - - --- 2023-08-28 Chanho Park Andes Changes Requested
[v2,1/3] riscv: bootstage: correct bootstage_report guard bootstage support for risc-v - - 1 - --- 2023-08-28 Chanho Park Andes Changes Requested
spl: bootstage: move bootstage_stash before jumping to image spl: bootstage: move bootstage_stash before jumping to image - - - - --- 2023-08-28 Chanho Park Andes Superseded
[v6,4/4] configs: starfive: Disable SYS_MALLOC_CLEAR_ON_INIT by default arch: riscv: jh7110: Correctly zero L2 LIM - - 1 - --- 2023-08-24 Shengyu Qu Andes Accepted
[v6,3/4] riscv: cpu: jh7110: Imply SPL_SYS_MALLOC_CLEAR_ON_INIT arch: riscv: jh7110: Correctly zero L2 LIM - - 1 - --- 2023-08-24 Shengyu Qu Andes Accepted
[v6,2/4] dlmalloc: Add support for SPL_SYS_MALLOC_CLEAR_ON_INIT arch: riscv: jh7110: Correctly zero L2 LIM - - 1 - --- 2023-08-24 Shengyu Qu Andes Accepted
[v6,1/4] Kconfig: Add SPL_SYS_MALLOC_CLEAR_ON_INIT arch: riscv: jh7110: Correctly zero L2 LIM - - 1 - --- 2023-08-24 Shengyu Qu Andes Accepted
[v5,3/3] riscv: cpu: jh7110: Imply SPL_SYS_MALLOC_CLEAR_ON_INIT arch: riscv: jh7110: Correctly zero L2 LIM - - - - --- 2023-08-23 Shengyu Qu Andes Changes Requested
[v5,2/3] dlmalloc: Add support for SPL_SYS_MALLOC_CLEAR_ON_INIT arch: riscv: jh7110: Correctly zero L2 LIM - - 1 - --- 2023-08-23 Shengyu Qu Andes Changes Requested
[v5,1/3] Kconfig: Add SPL_SYS_MALLOC_CLEAR_ON_INIT arch: riscv: jh7110: Correctly zero L2 LIM - - - - --- 2023-08-23 Shengyu Qu Andes Changes Requested
[v1,2/2] doc: board: starfive: Add more info about supported driver Enable PCIE and USB by default on Visionfive 2 - - - 2 --- 2023-08-22 Shengyu Qu Andes Accepted
[v1,1/2] configs: starfive: Enable PCIE auto enum and NVME/USB stuff for Starfive Visionfive 2 Enable PCIE and USB by default on Visionfive 2 - - - 2 --- 2023-08-22 Shengyu Qu Andes Accepted
[3/3] timer: riscv_aclint_timer: add timer_get_boot_us for BOOTSTAGE bootstage support for risc-v - - - - --- 2023-08-21 Chanho Park Andes Superseded
[2/3] riscv: timer: add timer_get_boot_us for BOOTSTAGE bootstage support for risc-v - - - - --- 2023-08-21 Chanho Park Andes Superseded
[1/3] riscv: bootstage: correct bootstage_report guard bootstage support for risc-v - - - - --- 2023-08-21 Chanho Park Andes Superseded
[2/2] risc-v: implement DBCN based debug console risc-v: implement DBCN based debug console - - 1 - --- 2023-08-19 Heinrich Schuchardt Andes Superseded
[1/2] risc-v: implement DBCN write byte risc-v: implement DBCN based debug console - - 1 - --- 2023-08-19 Heinrich Schuchardt Andes Superseded
[2/2] riscv: jh7110: enable riscv,timer in the device tree riscv: jh7110: visionfive2: fix u-boot crash due to missing timer - - 1 - --- 2023-08-14 Torsten Duwe Andes Accepted
[1/2] riscv: allow riscv timer to be instantiated via device tree riscv: jh7110: visionfive2: fix u-boot crash due to missing timer - - 1 - --- 2023-08-14 Torsten Duwe Andes Accepted
eeprom: starfive: set eth0 mac address properly eeprom: starfive: set eth0 mac address properly - - 1 - --- 2023-08-11 Seung-Woo Kim Andes Accepted
[v4,3/3] riscv: cpu: jh7110: Select SPL_ZERO_MEM_BEFORE_USE arch: riscv: jh7110: Correctly zero L2 LIM - - 1 - --- 2023-08-09 Shengyu Qu Andes Accepted
[v4,2/3] riscv: Add SPL_ZERO_MEM_BEFORE_USE implementation arch: riscv: jh7110: Correctly zero L2 LIM - - 1 - --- 2023-08-09 Shengyu Qu Andes Accepted
[v4,1/3] riscv: Kconfig: Add SPL_ZERO_MEM_BEFORE_USE arch: riscv: jh7110: Correctly zero L2 LIM - - 1 - --- 2023-08-09 Shengyu Qu Andes Accepted
riscv: Add Zbb support for building U-Boot riscv: Add Zbb support for building U-Boot - - 1 - --- 2023-08-09 Yu Chien Peter Lin Andes Accepted
[v1] configs: starfive: Enable environment in SPI flash support [v1] configs: starfive: Enable environment in SPI flash support - - 1 - --- 2023-08-08 Shengyu Qu Andes Accepted
[v3,3/3] riscv: cpu: jh7110: Select SPL_ZERO_MEM_BEFORE_USE arch: riscv: jh7110: Correctly zero L2 LIM - - 1 - --- 2023-08-08 Shengyu Qu Andes Superseded
[v3,2/3] riscv: Add SPL_ZERO_MEM_BEFORE_USE implementation arch: riscv: jh7110: Correctly zero L2 LIM - - - - --- 2023-08-08 Shengyu Qu Andes Superseded
[v3,1/3] riscv: Kconfig: Add SPL_ZERO_MEM_BEFORE_USE arch: riscv: jh7110: Correctly zero L2 LIM - - 1 - --- 2023-08-08 Shengyu Qu Andes Superseded
[v2,3/3] riscv: cpu: jh7110: Select SPL_ZERO_MEM_BEFORE_USE arch: riscv: jh7110: Correctly zero L2 LIM - - - - --- 2023-08-07 Shengyu Qu Andes Superseded
[v2,2/3] riscv: Add ZERO_MEM_BEFORE_USE implementation arch: riscv: jh7110: Correctly zero L2 LIM - - - - --- 2023-08-07 Shengyu Qu Andes Superseded
[v2,1/3] riscv: Kconfig: Add SPL_ZERO_MEM_BEFORE_USE arch: riscv: jh7110: Correctly zero L2 LIM - - - - --- 2023-08-07 Shengyu Qu Andes Superseded
[RESEND,v1,4/4] configs: riscv: starfive: Add VF2 PCIe USB3 XHCI support Add StarFive VF2 USB host support. - - 1 - --- 2023-08-07 Minda Chen Andes Accepted
[RESEND,v1,3/4] riscv: starfive: Add SYS_CACHE_SHIFT_6 to enable SYS_CACHELINE_SIZE Add StarFive VF2 USB host support. - - 2 - --- 2023-08-07 Minda Chen Andes Accepted
[RESEND,v1,2/4] riscv: dts: starfive: Enable pcie0 dts node Add StarFive VF2 USB host support. - - 1 - --- 2023-08-07 Minda Chen Andes Accepted
[RESEND,v1,1/4] pci: plda: Get correct ECAM offset in multiple PCIe RC case Add StarFive VF2 USB host support. - - 1 - --- 2023-08-07 Minda Chen Andes Accepted
[v1,4/4] configs: riscv: starfive: Add VF2 PCIe XHCI config support Add VF2 USB host support. - - - - --- 2023-08-03 Minda Chen Andes Superseded
[v1,2/4] riscv: dts: starfive: Enable pcie0 dts node Add VF2 USB host support. - - - - --- 2023-08-03 Minda Chen Andes Superseded
[v1,1/4] pci: plda: Get correct ECAM offset in multiple PCIe RC case Add VF2 USB host support. - - - - --- 2023-08-03 Minda Chen Andes Superseded
[1/1] cmd/sbi: display new extensions [1/1] cmd/sbi: display new extensions - - 1 - --- 2023-08-02 Heinrich Schuchardt Andes Accepted
[1/1] riscv: qemu: imply CONFIG_DM_RNG [1/1] riscv: qemu: imply CONFIG_DM_RNG - - 1 - --- 2023-07-28 Heinrich Schuchardt Andes Accepted
Remove unused parameters Remove unused parameters - - - - --- 2023-07-28 Shenlin Liang Andes Changes Requested
[v2,1/1] acpi: Add missing RISC-V acpi_table header [v2,1/1] acpi: Add missing RISC-V acpi_table header - - 1 - --- 2023-07-26 Heinrich Schuchardt Andes Accepted
[1/1] riscv: sifive: initialize PCI on Unmatched [1/1] riscv: sifive: initialize PCI on Unmatched - - 1 - --- 2023-07-25 Heinrich Schuchardt Andes Accepted
[v8,4/4] riscv: dts: starfive: Enable PCIe host controller Add StarFive JH7110 PCIe drvier support - - 1 - --- 2023-07-25 Minda Chen Andes Accepted
[v8,3/4] configs: starfive-jh7110: Add support for PCIe host driver Add StarFive JH7110 PCIe drvier support - - 1 - --- 2023-07-25 Minda Chen Andes Accepted
[v8,2/4] starfive: pci: Add StarFive JH7110 pcie driver Add StarFive JH7110 PCIe drvier support 1 - 1 - --- 2023-07-25 Minda Chen Andes Accepted
[v8,1/4] i2c: designware: Add Kconfig for designware_i2c_pci.c Add StarFive JH7110 PCIe drvier support - - 2 - --- 2023-07-25 Minda Chen Andes Accepted
[1/1] acpi: Add missing RISC-V acpi_table header [1/1] acpi: Add missing RISC-V acpi_table header - - - - --- 2023-07-25 Heinrich Schuchardt Andes Superseded
[18/18] riscv: qemu: Enable usb keyboard as an input device video: bochs: Remove the x86 limitation - - 2 - --- 2023-07-23 Bin Meng Andes Accepted
[17/18] riscv: qemu: Remove out-of-date "riscv, kernel-start" handling video: bochs: Remove the x86 limitation - - 2 - --- 2023-07-23 Bin Meng Andes Accepted
[16/18] riscv: define a cache line size for the generic CPU video: bochs: Remove the x86 limitation - - 1 - --- 2023-07-23 Bin Meng Andes Accepted
[15/18] riscv: qemu: Enable PRE_CONSOLE_BUFFER video: bochs: Remove the x86 limitation - - 2 - --- 2023-07-23 Bin Meng Andes Accepted
[14/18] console: Print out complete stdio device list video: bochs: Remove the x86 limitation - - 2 - --- 2023-07-23 Bin Meng Andes Accepted
[13/18] console: Refactor stdio_print_current_devices() a little bit video: bochs: Remove the x86 limitation - - - - --- 2023-07-23 Bin Meng Andes Accepted
[12/18] console: Make stdio_print_current_devices() static video: bochs: Remove the x86 limitation - - 1 1 --- 2023-07-23 Bin Meng Andes Accepted
[11/18] console: kconfig: Drop the redundant VIDEO dependency video: bochs: Remove the x86 limitation - - 2 - --- 2023-07-23 Bin Meng Andes Accepted
[10/18] riscv: qemu: Enable Bochs video support video: bochs: Remove the x86 limitation - - 1 - --- 2023-07-23 Bin Meng Andes Accepted
[1/1] riscv: qemu: provide more SPL boot methods [1/1] riscv: qemu: provide more SPL boot methods - - - - --- 2023-07-22 Heinrich Schuchardt Andes New
[v2,1/1] riscv: define a cache line size for the generic CPU [v2,1/1] riscv: define a cache line size for the generic CPU - - 1 - --- 2023-07-21 Heinrich Schuchardt Andes Accepted
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