| Message ID | 20180124051407.19673-1-vigneshr@ti.com |
|---|---|
| Headers | show |
| Series | cadence-quadspi: Fix issues with non 32bit aligned accesses | expand |
On Wed, Jan 24, 2018 at 10:44 AM, Vignesh R <vigneshr@ti.com> wrote: > This series reverts use of bounce_buf.c for non-DMA related alignment > restriction and replaces it with local bounce buffer to handle problems > with non 32 bit aligned writes on TI platforms. > Based on top of Jason's series: > [PATCH v6 0/4] spi: cadence_spi: Adopt Linux DT bindings > > Tested on K2G EVM. > > v3: > Rebased on top of latest u-boot-spi/master changes. > > Goldschmidt Simon (1): > Revert "spi: cadence_qspi_apb: Use 32 bit indirect read transaction > when possible" > > Vignesh R (2): > Revert "spi: cadence_qspi_apb: Use 32 bit indirect write transaction > when possible" > spi: cadence_qspi_apb: Make flash writes 32 bit aligned Applied to u-boot-spi/master, thanks!
This series reverts use of bounce_buf.c for non-DMA related alignment restriction and replaces it with local bounce buffer to handle problems with non 32 bit aligned writes on TI platforms. Based on top of Jason's series: [PATCH v6 0/4] spi: cadence_spi: Adopt Linux DT bindings Tested on K2G EVM. v3: Rebased on top of latest u-boot-spi/master changes. Goldschmidt Simon (1): Revert "spi: cadence_qspi_apb: Use 32 bit indirect read transaction when possible" Vignesh R (2): Revert "spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible" spi: cadence_qspi_apb: Make flash writes 32 bit aligned drivers/spi/cadence_qspi_apb.c | 53 ++++++++++++++++++++-------------------- include/configs/k2g_evm.h | 1 - include/configs/socfpga_common.h | 1 - include/configs/stv0991.h | 1 - 4 files changed, 26 insertions(+), 30 deletions(-)