From patchwork Wed Jan 24 05:14:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 865177 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="JHaYqKkm"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zRD153Spsz9rxj for ; Wed, 24 Jan 2018 16:16:41 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 279DCC2217B; Wed, 24 Jan 2018 05:14:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 9AC5CC2217F; Wed, 24 Jan 2018 05:14:35 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id A6471C21F0B; Wed, 24 Jan 2018 05:14:12 +0000 (UTC) Received: from fllnx209.ext.ti.com (fllnx209.ext.ti.com [198.47.19.16]) by lists.denx.de (Postfix) with ESMTPS id BA6E0C21E5B for ; Wed, 24 Jan 2018 05:14:08 +0000 (UTC) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id w0O5DkwF004428; Tue, 23 Jan 2018 23:13:46 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1516770826; bh=2aQqLJxJr2wMR71EQlLKJl6ximJWM/LmUeawhYy4hOA=; h=From:To:CC:Subject:Date; b=JHaYqKkmsfN8n3K9dhil4ks7G4Ae4IJ0dpxeClZWRpNds18/j/+sBaW7BJX+vygkq qj/SSG5q2UyNYJQeP/HZyJOr1wtlS0e+2ACt743fjb86W+JKuGJaN/AzFP4/W39Otx u0VgrcfSn1bc0cEOD2XbuZASGeoh4wLyvON2okY0= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w0O5DkmT000855; Tue, 23 Jan 2018 23:13:46 -0600 Received: from DLEE101.ent.ti.com (157.170.170.31) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Tue, 23 Jan 2018 23:13:46 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Tue, 23 Jan 2018 23:13:46 -0600 Received: from a0132425.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w0O5Di4N012216; Tue, 23 Jan 2018 23:13:44 -0600 From: Vignesh R To: Jagan Teki Date: Wed, 24 Jan 2018 10:44:04 +0530 Message-ID: <20180124051407.19673-1-vigneshr@ti.com> X-Mailer: git-send-email 2.16.0 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: Marek Vasut , Jason Rush , u-boot@lists.denx.de Subject: [U-Boot] [PATCH v3 0/3] cadence-quadspi: Fix issues with non 32bit aligned accesses X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This series reverts use of bounce_buf.c for non-DMA related alignment restriction and replaces it with local bounce buffer to handle problems with non 32 bit aligned writes on TI platforms. Based on top of Jason's series: [PATCH v6 0/4] spi: cadence_spi: Adopt Linux DT bindings Tested on K2G EVM. v3: Rebased on top of latest u-boot-spi/master changes. Goldschmidt Simon (1): Revert "spi: cadence_qspi_apb: Use 32 bit indirect read transaction when possible" Vignesh R (2): Revert "spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible" spi: cadence_qspi_apb: Make flash writes 32 bit aligned drivers/spi/cadence_qspi_apb.c | 53 ++++++++++++++++++++-------------------- include/configs/k2g_evm.h | 1 - include/configs/socfpga_common.h | 1 - include/configs/stv0991.h | 1 - 4 files changed, 26 insertions(+), 30 deletions(-)