| Message ID | 20230105221251.17896-4-eiakovlev@linux.microsoft.com |
|---|---|
| State | New |
| Headers | show |
| Series | various aarch64 fixes for running Hyper-V on TCG | expand |
On Thu, 5 Jan 2023 at 22:13, Evgeny Iakovlev <eiakovlev@linux.microsoft.com> wrote: > > ARM trusted firmware, when built with FEAT_HCX support, sets SCR_EL3.HXEn bit > to allow EL2 to modify HCRX_EL2 register without trapping it in EL3. Qemu > uses a valid mask to clear unsupported SCR_EL3 bits when emulating SCR_EL3 > write, and that mask doesn't include SCR_EL3.HXEn bit even if FEAT_HCX is > enabled and exposed to the guest. As a result EL3 writes of that bit are > ignored. > > Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com> > --- > target/arm/helper.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index bac2ea62c4..962affdd52 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -1844,6 +1844,9 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) > if (cpu_isar_feature(aa64_sme, cpu)) { > valid_mask |= SCR_ENTP2; > } > + if (cpu_isar_feature(aa64_hcx, cpu)) { > + valid_mask |= SCR_HXEN; > + } > } else { > valid_mask &= ~(SCR_RW | SCR_ST); > if (cpu_isar_feature(aa32_ras, cpu)) { > -- Oops. This is worth Cc: qemu-stable@nongnu.org I think. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> I'll take this 3rd patch into target-arm.next now; I've left review comments for the other 2. thanks -- PMM
On 1/13/2023 14:20, Peter Maydell wrote: > On Thu, 5 Jan 2023 at 22:13, Evgeny Iakovlev > <eiakovlev@linux.microsoft.com> wrote: >> ARM trusted firmware, when built with FEAT_HCX support, sets SCR_EL3.HXEn bit >> to allow EL2 to modify HCRX_EL2 register without trapping it in EL3. Qemu >> uses a valid mask to clear unsupported SCR_EL3 bits when emulating SCR_EL3 >> write, and that mask doesn't include SCR_EL3.HXEn bit even if FEAT_HCX is >> enabled and exposed to the guest. As a result EL3 writes of that bit are >> ignored. >> >> Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com> >> --- >> target/arm/helper.c | 3 +++ >> 1 file changed, 3 insertions(+) >> >> diff --git a/target/arm/helper.c b/target/arm/helper.c >> index bac2ea62c4..962affdd52 100644 >> --- a/target/arm/helper.c >> +++ b/target/arm/helper.c >> @@ -1844,6 +1844,9 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) >> if (cpu_isar_feature(aa64_sme, cpu)) { >> valid_mask |= SCR_ENTP2; >> } >> + if (cpu_isar_feature(aa64_hcx, cpu)) { >> + valid_mask |= SCR_HXEN; >> + } >> } else { >> valid_mask &= ~(SCR_RW | SCR_ST); >> if (cpu_isar_feature(aa32_ras, cpu)) { >> -- > Oops. This is worth > Cc: qemu-stable@nongnu.org > > I think. > > Reviewed-by: Peter Maydell <peter.maydell@linaro.org> > > I'll take this 3rd patch into target-arm.next now; I've left > review comments for the other 2. > > thanks > -- PMM Thanks, Peter! I'll be addressing the comments today and post a v2 with changes for the first 2.
diff --git a/target/arm/helper.c b/target/arm/helper.c index bac2ea62c4..962affdd52 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1844,6 +1844,9 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) if (cpu_isar_feature(aa64_sme, cpu)) { valid_mask |= SCR_ENTP2; } + if (cpu_isar_feature(aa64_hcx, cpu)) { + valid_mask |= SCR_HXEN; + } } else { valid_mask &= ~(SCR_RW | SCR_ST); if (cpu_isar_feature(aa32_ras, cpu)) {
ARM trusted firmware, when built with FEAT_HCX support, sets SCR_EL3.HXEn bit to allow EL2 to modify HCRX_EL2 register without trapping it in EL3. Qemu uses a valid mask to clear unsupported SCR_EL3 bits when emulating SCR_EL3 write, and that mask doesn't include SCR_EL3.HXEn bit even if FEAT_HCX is enabled and exposed to the guest. As a result EL3 writes of that bit are ignored. Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com> --- target/arm/helper.c | 3 +++ 1 file changed, 3 insertions(+)