| Message ID | 20230105221251.17896-3-eiakovlev@linux.microsoft.com |
|---|---|
| State | New |
| Headers | show |
| Series | various aarch64 fixes for running Hyper-V on TCG | expand |
On Thu, 5 Jan 2023 at 22:13, Evgeny Iakovlev <eiakovlev@linux.microsoft.com> wrote: > > Qemu doesn't implement Debug Communication Channel, however when running > Microsoft Hyper-V in software-emulated ARM64 as a guest, it tries to > access some of the DCM registers during an EL2 context switch. I've occasionally thought about implementing the DCC as something the QEMU user could connect to a QEMU chardev. But that would be a lot of faff for no very obvious benefit, so making these registers RAZ makes sense for now. > Provide RAZ/WI stubs for OSDTRRX_EL1, OSDTRTX_EL1 and OSECCR_EL1 > registers in the same way the rest of DCM is currently done. Do > account for access traps though with access_tda. OSECCR_EL1 isn't part of DCC; it's a different bit of the external debug interface. > Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com> > --- > target/arm/debug_helper.c | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c > index b244e146e2..2a7c3d7e38 100644 > --- a/target/arm/debug_helper.c > +++ b/target/arm/debug_helper.c > @@ -673,6 +673,18 @@ static const ARMCPRegInfo debug_cp_reginfo[] = { > .opc0 = 2, .opc1 = 3, .crn = 0, .crm = 1, .opc2 = 0, > .access = PL0_R, .accessfn = access_tda, > .type = ARM_CP_CONST, .resetvalue = 0 }, > + { .name = "OSDTRRX_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14, > + .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 2, > + .access = PL1_RW, .accessfn = access_tda, > + .type = ARM_CP_CONST, .resetvalue = 0 }, > + { .name = "OSDTRTX_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14, > + .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2, > + .access = PL1_RW, .accessfn = access_tda, > + .type = ARM_CP_CONST, .resetvalue = 0 }, > + { .name = "OSECCR_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14, > + .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2, > + .access = PL1_RW, .accessfn = access_tda, > + .type = ARM_CP_CONST, .resetvalue = 0 }, A brief comment or two here would be nice. Otherwise Reviewed-by: Peter Maydell <peter.maydell@linaro.org> thanks -- PMM
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index b244e146e2..2a7c3d7e38 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -673,6 +673,18 @@ static const ARMCPRegInfo debug_cp_reginfo[] = { .opc0 = 2, .opc1 = 3, .crn = 0, .crm = 1, .opc2 = 0, .access = PL0_R, .accessfn = access_tda, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "OSDTRRX_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14, + .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 2, + .access = PL1_RW, .accessfn = access_tda, + .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "OSDTRTX_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14, + .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2, + .access = PL1_RW, .accessfn = access_tda, + .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "OSECCR_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14, + .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2, + .access = PL1_RW, .accessfn = access_tda, + .type = ARM_CP_CONST, .resetvalue = 0 }, /* * DBGDSCRint[15,12,5:2] map to MDSCR_EL1[15,12,5:2]. Map all bits as * it is unlikely a guest will care.
Qemu doesn't implement Debug Communication Channel, however when running Microsoft Hyper-V in software-emulated ARM64 as a guest, it tries to access some of the DCM registers during an EL2 context switch. Provide RAZ/WI stubs for OSDTRRX_EL1, OSDTRTX_EL1 and OSECCR_EL1 registers in the same way the rest of DCM is currently done. Do account for access traps though with access_tda. Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com> --- target/arm/debug_helper.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)