diff mbox series

[v2,4/8] target/riscv: debug: Restrict the range of tselect value can be written

Message ID 20220909134215.1843865-5-bmeng.cn@gmail.com
State New
Headers show
Series target/riscv: Improve RISC-V Debug support | expand

Commit Message

Bin Meng Sept. 9, 2022, 1:42 p.m. UTC 
From: Frank Chang <frank.chang@sifive.com>

The value of tselect CSR can be written should be limited within the
range of supported triggers number.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

(no changes since v1)

 target/riscv/debug.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

Comments

LIU Zhiwei Sept. 16, 2022, 1:59 a.m. UTC | #1 
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>

Zhiwei

On 2022/9/9 21:42, Bin Meng wrote:
> From: Frank Chang <frank.chang@sifive.com>
>
> The value of tselect CSR can be written should be limited within the
> range of supported triggers number.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> (no changes since v1)
>
>   target/riscv/debug.c | 9 +++------
>   1 file changed, 3 insertions(+), 6 deletions(-)
>
> diff --git a/target/riscv/debug.c b/target/riscv/debug.c
> index 06feef7d67..d6666164cd 100644
> --- a/target/riscv/debug.c
> +++ b/target/riscv/debug.c
> @@ -127,10 +127,6 @@ bool tdata_available(CPURISCVState *env, int tdata_index)
>           return false;
>       }
>   
> -    if (unlikely(env->trigger_cur >= RV_MAX_TRIGGERS)) {
> -        return false;
> -    }
> -
>       return tdata_mapping[trigger_type][tdata_index];
>   }
>   
> @@ -141,8 +137,9 @@ target_ulong tselect_csr_read(CPURISCVState *env)
>   
>   void tselect_csr_write(CPURISCVState *env, target_ulong val)
>   {
> -    /* all target_ulong bits of tselect are implemented */
> -    env->trigger_cur = val;
> +    if (val < RV_MAX_TRIGGERS) {
> +        env->trigger_cur = val;
> +    }
>   }
>   
>   static target_ulong tdata1_validate(CPURISCVState *env, target_ulong val,
diff mbox series

Patch

diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index 06feef7d67..d6666164cd 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -127,10 +127,6 @@  bool tdata_available(CPURISCVState *env, int tdata_index)
         return false;
     }
 
-    if (unlikely(env->trigger_cur >= RV_MAX_TRIGGERS)) {
-        return false;
-    }
-
     return tdata_mapping[trigger_type][tdata_index];
 }
 
@@ -141,8 +137,9 @@  target_ulong tselect_csr_read(CPURISCVState *env)
 
 void tselect_csr_write(CPURISCVState *env, target_ulong val)
 {
-    /* all target_ulong bits of tselect are implemented */
-    env->trigger_cur = val;
+    if (val < RV_MAX_TRIGGERS) {
+        env->trigger_cur = val;
+    }
 }
 
 static target_ulong tdata1_validate(CPURISCVState *env, target_ulong val,