| Message ID | 20220909134215.1843865-6-bmeng.cn@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | target/riscv: Improve RISC-V Debug support | expand |
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Zhiwei On 2022/9/9 21:42, Bin Meng wrote: > From: Frank Chang <frank.chang@sifive.com> > > tinfo.info: > One bit for each possible type enumerated in tdata1. > If the bit is set, then that type is supported by the currently > selected trigger. > > Signed-off-by: Frank Chang <frank.chang@sifive.com> > Reviewed-by: Bin Meng <bmeng.cn@gmail.com> > Signed-off-by: Bin Meng <bmeng.cn@gmail.com> > --- > > (no changes since v1) > > target/riscv/cpu_bits.h | 1 + > target/riscv/debug.h | 2 ++ > target/riscv/csr.c | 8 ++++++++ > target/riscv/debug.c | 10 +++++++--- > 4 files changed, 18 insertions(+), 3 deletions(-) > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > index 7be12cac2e..1972aee3bb 100644 > --- a/target/riscv/cpu_bits.h > +++ b/target/riscv/cpu_bits.h > @@ -321,6 +321,7 @@ > #define CSR_TDATA1 0x7a1 > #define CSR_TDATA2 0x7a2 > #define CSR_TDATA3 0x7a3 > +#define CSR_TINFO 0x7a4 > > /* Debug Mode Registers */ > #define CSR_DCSR 0x7b0 > diff --git a/target/riscv/debug.h b/target/riscv/debug.h > index 76146f373a..9f69c64591 100644 > --- a/target/riscv/debug.h > +++ b/target/riscv/debug.h > @@ -95,6 +95,8 @@ void tselect_csr_write(CPURISCVState *env, target_ulong val); > target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index); > void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val); > > +target_ulong tinfo_csr_read(CPURISCVState *env); > + > void riscv_cpu_debug_excp_handler(CPUState *cs); > bool riscv_cpu_debug_check_breakpoint(CPUState *cs); > bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 3d0d8e0340..e66019048d 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -3089,6 +3089,13 @@ static RISCVException write_tdata(CPURISCVState *env, int csrno, > return RISCV_EXCP_NONE; > } > > +static RISCVException read_tinfo(CPURISCVState *env, int csrno, > + target_ulong *val) > +{ > + *val = tinfo_csr_read(env); > + return RISCV_EXCP_NONE; > +} > + > /* > * Functions to access Pointer Masking feature registers > * We have to check if current priv lvl could modify > @@ -3893,6 +3900,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > [CSR_TDATA1] = { "tdata1", debug, read_tdata, write_tdata }, > [CSR_TDATA2] = { "tdata2", debug, read_tdata, write_tdata }, > [CSR_TDATA3] = { "tdata3", debug, read_tdata, write_tdata }, > + [CSR_TINFO] = { "tinfo", debug, read_tinfo, write_ignore }, > > /* User Pointer Masking */ > [CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte }, > diff --git a/target/riscv/debug.c b/target/riscv/debug.c > index d6666164cd..7d546ace42 100644 > --- a/target/riscv/debug.c > +++ b/target/riscv/debug.c > @@ -37,9 +37,7 @@ > * - tdata1 > * - tdata2 > * - tdata3 > - * > - * We don't support writable 'type' field in the tdata1 register, so there is > - * no need to implement the "tinfo" CSR. > + * - tinfo > * > * The following triggers are implemented: > * > @@ -372,6 +370,12 @@ void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val) > } > } > > +target_ulong tinfo_csr_read(CPURISCVState *env) > +{ > + /* assume all triggers support the same types of triggers */ > + return BIT(TRIGGER_TYPE_AD_MATCH); > +} > + > void riscv_cpu_debug_excp_handler(CPUState *cs) > { > RISCVCPU *cpu = RISCV_CPU(cs);
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 7be12cac2e..1972aee3bb 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -321,6 +321,7 @@ #define CSR_TDATA1 0x7a1 #define CSR_TDATA2 0x7a2 #define CSR_TDATA3 0x7a3 +#define CSR_TINFO 0x7a4 /* Debug Mode Registers */ #define CSR_DCSR 0x7b0 diff --git a/target/riscv/debug.h b/target/riscv/debug.h index 76146f373a..9f69c64591 100644 --- a/target/riscv/debug.h +++ b/target/riscv/debug.h @@ -95,6 +95,8 @@ void tselect_csr_write(CPURISCVState *env, target_ulong val); target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index); void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val); +target_ulong tinfo_csr_read(CPURISCVState *env); + void riscv_cpu_debug_excp_handler(CPUState *cs); bool riscv_cpu_debug_check_breakpoint(CPUState *cs); bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 3d0d8e0340..e66019048d 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3089,6 +3089,13 @@ static RISCVException write_tdata(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } +static RISCVException read_tinfo(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val = tinfo_csr_read(env); + return RISCV_EXCP_NONE; +} + /* * Functions to access Pointer Masking feature registers * We have to check if current priv lvl could modify @@ -3893,6 +3900,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_TDATA1] = { "tdata1", debug, read_tdata, write_tdata }, [CSR_TDATA2] = { "tdata2", debug, read_tdata, write_tdata }, [CSR_TDATA3] = { "tdata3", debug, read_tdata, write_tdata }, + [CSR_TINFO] = { "tinfo", debug, read_tinfo, write_ignore }, /* User Pointer Masking */ [CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte }, diff --git a/target/riscv/debug.c b/target/riscv/debug.c index d6666164cd..7d546ace42 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -37,9 +37,7 @@ * - tdata1 * - tdata2 * - tdata3 - * - * We don't support writable 'type' field in the tdata1 register, so there is - * no need to implement the "tinfo" CSR. + * - tinfo * * The following triggers are implemented: * @@ -372,6 +370,12 @@ void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val) } } +target_ulong tinfo_csr_read(CPURISCVState *env) +{ + /* assume all triggers support the same types of triggers */ + return BIT(TRIGGER_TYPE_AD_MATCH); +} + void riscv_cpu_debug_excp_handler(CPUState *cs) { RISCVCPU *cpu = RISCV_CPU(cs);