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[PULL,22/41] target/ppc: 405: Alignment exception cleanup

Message ID 20220131110811.619053-23-clg@kaod.org
State New
Headers show
Series [PULL,01/41] spapr: Force 32bit when resetting a core | expand

Commit Message

Cédric Le Goater Jan. 31, 2022, 11:07 a.m. UTC 
From: Fabiano Rosas <farosas@linux.ibm.com>

There is no DSISR in the 405. It uses DEAR which we already set
earlier at ppc_cpu_do_unaligned_access.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au
Message-Id: <20220118184448.852996-10-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 target/ppc/excp_helper.c | 7 -------
 1 file changed, 7 deletions(-)
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Patch

diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 1f915f607d8f..55f6b0e98100 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -474,13 +474,6 @@  static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
     case POWERPC_EXCP_EXTERNAL:  /* External input                           */
         break;
     case POWERPC_EXCP_ALIGN:     /* Alignment exception                      */
-        /* Get rS/rD and rA from faulting opcode */
-        /*
-         * Note: the opcode fields will not be set properly for a
-         * direct store load/store, but nobody cares as nobody
-         * actually uses direct store segments.
-         */
-        env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16;
         break;
     case POWERPC_EXCP_PROGRAM:   /* Program exception                        */
         switch (env->error_code & ~0xF) {