diff mbox series

[PULL,15/41] target/ppc: 405: Add missing MSR_ME bit

Message ID 20220131110811.619053-16-clg@kaod.org
State New
Headers show
Series [PULL,01/41] spapr: Force 32bit when resetting a core | expand

Commit Message

Cédric Le Goater Jan. 31, 2022, 11:07 a.m. UTC 
From: Fabiano Rosas <farosas@linux.ibm.com>

The 405 MSR has the Machine Check Enable bit. We're making use of it
when dispatching Machine Check, so add the bit to the msr_mask.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220118184448.852996-3-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 target/ppc/cpu_init.c | 1 +
 1 file changed, 1 insertion(+)
diff mbox series

Patch

diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index e63705b1c6b2..23a13036b211 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -2540,6 +2540,7 @@  POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
                     (1ull << MSR_EE) |
                     (1ull << MSR_PR) |
                     (1ull << MSR_FP) |
+                    (1ull << MSR_ME) |
                     (1ull << MSR_DWE) |
                     (1ull << MSR_DE) |
                     (1ull << MSR_IR) |