diff mbox series

[PULL,14/41] target/ppc: 405: Rename MSR_POW to MSR_WE

Message ID 20220131110811.619053-15-clg@kaod.org
State New
Headers show
Series [PULL,01/41] spapr: Force 32bit when resetting a core | expand

Commit Message

Cédric Le Goater Jan. 31, 2022, 11:07 a.m. UTC 
From: Fabiano Rosas <farosas@linux.ibm.com>

Bit 13 is the Wait State Enable bit. Give it its proper name.

As far as I can see we don't do anything with MSR_POW for the 405, so
this change has no effect.

Suggested-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220118184448.852996-2-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 target/ppc/cpu.h      | 1 +
 target/ppc/cpu_init.c | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 2560b70c5f10..66e13075c3df 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -327,6 +327,7 @@  typedef enum {
 #define MSR_S    22 /* Secure state                                          */
 #define MSR_KEY  19 /* key bit on 603e                                       */
 #define MSR_POW  18 /* Power management                                      */
+#define MSR_WE   18 /* Wait State Enable on 405                              */
 #define MSR_TGPR 17 /* TGPR usage on 602/603                        x        */
 #define MSR_CE   17 /* Critical interrupt enable on embedded PowerPC x       */
 #define MSR_ILE  16 /* Interrupt little-endian mode                          */
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index e30e86fe9d04..e63705b1c6b2 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -2535,7 +2535,7 @@  POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
                        PPC_MEM_SYNC | PPC_MEM_EIEIO |
                        PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
                        PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
-    pcc->msr_mask = (1ull << MSR_POW) |
+    pcc->msr_mask = (1ull << MSR_WE) |
                     (1ull << MSR_CE) |
                     (1ull << MSR_EE) |
                     (1ull << MSR_PR) |