diff mbox series

[v4,04/10] target/arm: Split arm_pre_translate_insn

Message ID 20211103040352.373688-5-richard.henderson@linaro.org
State New
Headers show
Series target/arm: Fix insn exception priorities | expand

Commit Message

Richard Henderson Nov. 3, 2021, 4:03 a.m. UTC 
Create arm_check_ss_active and arm_check_kernelpage.

Reverse the order of the tests.  While it doesn't matter in practice,
because only user-only has a kernel page and user-only never sets
ss_active, ss_active has priority over execution exceptions and it
is best to keep them in the proper order.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/translate.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

Comments

Peter Maydell Nov. 5, 2021, 5:06 p.m. UTC | #1 
On Wed, 3 Nov 2021 at 04:07, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Create arm_check_ss_active and arm_check_kernelpage.
>
> Reverse the order of the tests.  While it doesn't matter in practice,
> because only user-only has a kernel page and user-only never sets
> ss_active, ss_active has priority over execution exceptions and it
> is best to keep them in the proper order.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM
diff mbox series

Patch

diff --git a/target/arm/translate.c b/target/arm/translate.c
index a39456ea98..82d4e24c27 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9513,7 +9513,7 @@  static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
     dc->insn_start = tcg_last_op();
 }
 
-static bool arm_pre_translate_insn(DisasContext *dc)
+static bool arm_check_kernelpage(DisasContext *dc)
 {
 #ifdef CONFIG_USER_ONLY
     /* Intercept jump to the magic kernel page.  */
@@ -9525,7 +9525,11 @@  static bool arm_pre_translate_insn(DisasContext *dc)
         return true;
     }
 #endif
+    return false;
+}
 
+static bool arm_check_ss_active(DisasContext *dc)
+{
     if (dc->ss_active && !dc->pstate_ss) {
         /* Singlestep state is Active-pending.
          * If we're in this state at the start of a TB then either
@@ -9562,7 +9566,7 @@  static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
     uint32_t pc = dc->base.pc_next;
     unsigned int insn;
 
-    if (arm_pre_translate_insn(dc)) {
+    if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) {
         dc->base.pc_next = pc + 4;
         return;
     }
@@ -9633,7 +9637,7 @@  static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
     uint32_t insn;
     bool is_16bit;
 
-    if (arm_pre_translate_insn(dc)) {
+    if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) {
         dc->base.pc_next = pc + 2;
         return;
     }