Message ID | 20211103040352.373688-6-richard.henderson@linaro.org |
---|---|
State | New |
Headers | show |
Series | target/arm: Fix insn exception priorities | expand |
On Wed, 3 Nov 2021 at 04:09, Richard Henderson <richard.henderson@linaro.org> wrote: > > The size of the code covered by a TranslationBlock cannot be 0; > this is checked via assert in tb_gen_code. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/arm/translate-a64.c | 1 + > 1 file changed, 1 insertion(+) > Reviewed-by: Peter Maydell <peter.maydell@linaro.org> thanks -- PMM
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 9c4258ccac..2986fe1393 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14767,6 +14767,7 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) assert(s->base.num_insns == 1); gen_swstep_exception(s, 0, 0); s->base.is_jmp = DISAS_NORETURN; + s->base.pc_next = pc + 4; return; }
The size of the code covered by a TranslationBlock cannot be 0; this is checked via assert in tb_gen_code. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/translate-a64.c | 1 + 1 file changed, 1 insertion(+)