@@ -340,6 +340,30 @@ void helper_store_mmcr0(CPUPPCState *env, target_ulong value)
} else {
start_cycle_count_session(env);
}
+ } else {
+ /*
+ * No change in MMCR0_FC state, but if the PMU is running and
+ * a change in the counter negative overflow bits is made,
+ * we need to restart a new cycle count session to restart
+ * the appropriate overflow timers.
+ */
+ if (curr_FC) {
+ return;
+ }
+
+ bool pmc1ce_curr = curr_value & MMCR0_PMC1CE;
+ bool pmc1ce_new = value & MMCR0_PMC1CE;
+ bool pmcjce_curr = curr_value & MMCR0_PMCjCE;
+ bool pmcjce_new = value & MMCR0_PMCjCE;
+
+ if (pmc1ce_curr == pmc1ce_new && pmcjce_curr == pmcjce_new) {
+ return;
+ }
+
+ /* Update the counter with the events counted so far */
+ update_cycles_PMCs(env);
+
+ start_cycle_count_session(env);
}
}
Up until this moment we were assuming that the counter negative enabled bits, PMC1CE and PMCjCE, would never be changed when the PMU is already started. Turns out that there is no such restriction in the PowerISA v3.1, and software can enable/disable overflow conditions of the counters at any time. To support this scenario, track the overflow bits state when a write in MMCR0 is made in which the run state of the PMU (MMCR0_FC bit) didn't change and, if some overflow bit were changed in the middle of a cycle count session, restart it. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> --- target/ppc/power8_pmu.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)