Message ID | 20210824163032.394099-4-danielhb413@gmail.com |
---|---|
State | New |
Headers | show |
Series | PMU-EBB support for PPC64 TCG | expand |
On Tue, Aug 24, 2021 at 01:30:19PM -0300, Daniel Henrique Barboza wrote: > From: Gustavo Romero <gromero@linux.ibm.com> > > Similar to the previous patch, user write on some PowerPC > PMU regs, in this case, MMCR0, is limited. Create a new > function to handle that. Ok.. ok, this fixes my concern on the previous patch. Best to avoid the confusing interim step though. I'm not sure there's a lot of use adding the general "group A" helper if you're going to replace them with more specific functions shortly afterwards. > > CC: Gustavo Romero <gustavo.romero@linaro.org> > Signed-off-by: Gustavo Romero <gromero@linux.ibm.com> > Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> > --- > target/ppc/cpu_init.c | 2 +- > target/ppc/spr_tcg.h | 1 + > target/ppc/translate.c | 38 ++++++++++++++++++++++++++++++++++++++ > 3 files changed, 40 insertions(+), 1 deletion(-) > > diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c > index 5510c3799f..860716da18 100644 > --- a/target/ppc/cpu_init.c > +++ b/target/ppc/cpu_init.c > @@ -6868,7 +6868,7 @@ static void register_book3s_pmu_sup_sprs(CPUPPCState *env) > static void register_book3s_pmu_user_sprs(CPUPPCState *env) > { > spr_register(env, SPR_POWER_UMMCR0, "UMMCR0", > - &spr_read_MMCR0_ureg, &spr_write_PMU_groupA_ureg, > + &spr_read_MMCR0_ureg, &spr_write_MMCR0_ureg, > &spr_read_ureg, &spr_write_ureg, > 0x00000000); > spr_register(env, SPR_POWER_UMMCR1, "UMMCR1", > diff --git a/target/ppc/spr_tcg.h b/target/ppc/spr_tcg.h > index 64ef2cd089..5c383dae3d 100644 > --- a/target/ppc/spr_tcg.h > +++ b/target/ppc/spr_tcg.h > @@ -43,6 +43,7 @@ void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn); > void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn); > void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn); > void spr_write_PMU_groupA_ureg(DisasContext *ctx, int sprn, int gprn); > +void spr_write_MMCR0_ureg(DisasContext *ctx, int sprn, int gprn); > > #ifndef CONFIG_USER_ONLY > void spr_write_generic32(DisasContext *ctx, int sprn, int gprn); > diff --git a/target/ppc/translate.c b/target/ppc/translate.c > index ec4160378d..b48eec83e3 100644 > --- a/target/ppc/translate.c > +++ b/target/ppc/translate.c > @@ -592,11 +592,49 @@ void spr_write_PMU_groupA_ureg(DisasContext *ctx, int sprn, int gprn) > } > spr_write_ureg(ctx, sprn, gprn); > } > + > +void spr_write_MMCR0_ureg(DisasContext *ctx, int sprn, int gprn) > +{ > + TCGv t0, t1; > + > + /* > + * MMCR0 is a Group A SPR. The same write access control > + * done in spr_write_PMU_groupA_ureg() applies. > + */ > + if (ctx->pmcc_clear) { > + gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); > + return; > + } > + > + t0 = tcg_temp_new(); > + t1 = tcg_temp_new(); > + > + /* > + * Filter out all bits but FC, PMAO, and PMAE, according > + * to ISA v3.1, in 10.4.4 Monitor Mode Control Register 0, > + * fourth paragraph. > + */ > + tcg_gen_andi_tl(t0, cpu_gpr[gprn], > + MMCR0_FC | MMCR0_PMAO | MMCR0_PMAE); > + gen_load_spr(t1, SPR_POWER_MMCR0); > + tcg_gen_andi_tl(t1, t1, ~(MMCR0_FC | MMCR0_PMAO | MMCR0_PMAE)); Since you're reusing them again here, definitely want a #define for this mask. > + /* Keep all other bits intact */ > + tcg_gen_or_tl(t1, t1, t0); > + gen_store_spr(SPR_POWER_MMCR0, t1); > + > + tcg_temp_free(t0); > + tcg_temp_free(t1); > +} > #else > void spr_write_PMU_groupA_ureg(DisasContext *ctx, int sprn, int gprn) > { > spr_noaccess(ctx, gprn, sprn); > } > + > +void spr_write_MMCR0_ureg(DisasContext *ctx, int sprn, int gprn) > +{ > + spr_noaccess(ctx, gprn, sprn); > +} > #endif > > /* SPR common to all non-embedded PowerPC */
On 8/25/21 1:37 AM, David Gibson wrote: > On Tue, Aug 24, 2021 at 01:30:19PM -0300, Daniel Henrique Barboza wrote: >> From: Gustavo Romero <gromero@linux.ibm.com> >> >> Similar to the previous patch, user write on some PowerPC >> PMU regs, in this case, MMCR0, is limited. Create a new >> function to handle that. > > Ok.. ok, this fixes my concern on the previous patch. Best to avoid > the confusing interim step though. I'm not sure there's a lot of use > adding the general "group A" helper if you're going to replace them > with more specific functions shortly afterwards. Perhaps we should merge patches 2 and 3 together. I'll also take into consideration that patch 15 will also add custom handling of more PMU regs and, perhaps, drop patch 1 entirely since the only control left for groupA will be MMCRA which can either be added separately or ignored (the kernel EBB tests doesn't bother with MMCRA permissions). Daniel > >> >> CC: Gustavo Romero <gustavo.romero@linaro.org> >> Signed-off-by: Gustavo Romero <gromero@linux.ibm.com> >> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> >> --- >> target/ppc/cpu_init.c | 2 +- >> target/ppc/spr_tcg.h | 1 + >> target/ppc/translate.c | 38 ++++++++++++++++++++++++++++++++++++++ >> 3 files changed, 40 insertions(+), 1 deletion(-) >> >> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c >> index 5510c3799f..860716da18 100644 >> --- a/target/ppc/cpu_init.c >> +++ b/target/ppc/cpu_init.c >> @@ -6868,7 +6868,7 @@ static void register_book3s_pmu_sup_sprs(CPUPPCState *env) >> static void register_book3s_pmu_user_sprs(CPUPPCState *env) >> { >> spr_register(env, SPR_POWER_UMMCR0, "UMMCR0", >> - &spr_read_MMCR0_ureg, &spr_write_PMU_groupA_ureg, >> + &spr_read_MMCR0_ureg, &spr_write_MMCR0_ureg, >> &spr_read_ureg, &spr_write_ureg, >> 0x00000000); >> spr_register(env, SPR_POWER_UMMCR1, "UMMCR1", >> diff --git a/target/ppc/spr_tcg.h b/target/ppc/spr_tcg.h >> index 64ef2cd089..5c383dae3d 100644 >> --- a/target/ppc/spr_tcg.h >> +++ b/target/ppc/spr_tcg.h >> @@ -43,6 +43,7 @@ void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn); >> void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn); >> void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn); >> void spr_write_PMU_groupA_ureg(DisasContext *ctx, int sprn, int gprn); >> +void spr_write_MMCR0_ureg(DisasContext *ctx, int sprn, int gprn); >> >> #ifndef CONFIG_USER_ONLY >> void spr_write_generic32(DisasContext *ctx, int sprn, int gprn); >> diff --git a/target/ppc/translate.c b/target/ppc/translate.c >> index ec4160378d..b48eec83e3 100644 >> --- a/target/ppc/translate.c >> +++ b/target/ppc/translate.c >> @@ -592,11 +592,49 @@ void spr_write_PMU_groupA_ureg(DisasContext *ctx, int sprn, int gprn) >> } >> spr_write_ureg(ctx, sprn, gprn); >> } >> + >> +void spr_write_MMCR0_ureg(DisasContext *ctx, int sprn, int gprn) >> +{ >> + TCGv t0, t1; >> + >> + /* >> + * MMCR0 is a Group A SPR. The same write access control >> + * done in spr_write_PMU_groupA_ureg() applies. >> + */ >> + if (ctx->pmcc_clear) { >> + gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); >> + return; >> + } >> + >> + t0 = tcg_temp_new(); >> + t1 = tcg_temp_new(); >> + >> + /* >> + * Filter out all bits but FC, PMAO, and PMAE, according >> + * to ISA v3.1, in 10.4.4 Monitor Mode Control Register 0, >> + * fourth paragraph. >> + */ >> + tcg_gen_andi_tl(t0, cpu_gpr[gprn], >> + MMCR0_FC | MMCR0_PMAO | MMCR0_PMAE); >> + gen_load_spr(t1, SPR_POWER_MMCR0); >> + tcg_gen_andi_tl(t1, t1, ~(MMCR0_FC | MMCR0_PMAO | MMCR0_PMAE)); > > Since you're reusing them again here, definitely want a #define for > this mask. > >> + /* Keep all other bits intact */ >> + tcg_gen_or_tl(t1, t1, t0); >> + gen_store_spr(SPR_POWER_MMCR0, t1); >> + >> + tcg_temp_free(t0); >> + tcg_temp_free(t1); >> +} >> #else >> void spr_write_PMU_groupA_ureg(DisasContext *ctx, int sprn, int gprn) >> { >> spr_noaccess(ctx, gprn, sprn); >> } >> + >> +void spr_write_MMCR0_ureg(DisasContext *ctx, int sprn, int gprn) >> +{ >> + spr_noaccess(ctx, gprn, sprn); >> +} >> #endif >> >> /* SPR common to all non-embedded PowerPC */ >
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 5510c3799f..860716da18 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6868,7 +6868,7 @@ static void register_book3s_pmu_sup_sprs(CPUPPCState *env) static void register_book3s_pmu_user_sprs(CPUPPCState *env) { spr_register(env, SPR_POWER_UMMCR0, "UMMCR0", - &spr_read_MMCR0_ureg, &spr_write_PMU_groupA_ureg, + &spr_read_MMCR0_ureg, &spr_write_MMCR0_ureg, &spr_read_ureg, &spr_write_ureg, 0x00000000); spr_register(env, SPR_POWER_UMMCR1, "UMMCR1", diff --git a/target/ppc/spr_tcg.h b/target/ppc/spr_tcg.h index 64ef2cd089..5c383dae3d 100644 --- a/target/ppc/spr_tcg.h +++ b/target/ppc/spr_tcg.h @@ -43,6 +43,7 @@ void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn); void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn); void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn); void spr_write_PMU_groupA_ureg(DisasContext *ctx, int sprn, int gprn); +void spr_write_MMCR0_ureg(DisasContext *ctx, int sprn, int gprn); #ifndef CONFIG_USER_ONLY void spr_write_generic32(DisasContext *ctx, int sprn, int gprn); diff --git a/target/ppc/translate.c b/target/ppc/translate.c index ec4160378d..b48eec83e3 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -592,11 +592,49 @@ void spr_write_PMU_groupA_ureg(DisasContext *ctx, int sprn, int gprn) } spr_write_ureg(ctx, sprn, gprn); } + +void spr_write_MMCR0_ureg(DisasContext *ctx, int sprn, int gprn) +{ + TCGv t0, t1; + + /* + * MMCR0 is a Group A SPR. The same write access control + * done in spr_write_PMU_groupA_ureg() applies. + */ + if (ctx->pmcc_clear) { + gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); + return; + } + + t0 = tcg_temp_new(); + t1 = tcg_temp_new(); + + /* + * Filter out all bits but FC, PMAO, and PMAE, according + * to ISA v3.1, in 10.4.4 Monitor Mode Control Register 0, + * fourth paragraph. + */ + tcg_gen_andi_tl(t0, cpu_gpr[gprn], + MMCR0_FC | MMCR0_PMAO | MMCR0_PMAE); + gen_load_spr(t1, SPR_POWER_MMCR0); + tcg_gen_andi_tl(t1, t1, ~(MMCR0_FC | MMCR0_PMAO | MMCR0_PMAE)); + /* Keep all other bits intact */ + tcg_gen_or_tl(t1, t1, t0); + gen_store_spr(SPR_POWER_MMCR0, t1); + + tcg_temp_free(t0); + tcg_temp_free(t1); +} #else void spr_write_PMU_groupA_ureg(DisasContext *ctx, int sprn, int gprn) { spr_noaccess(ctx, gprn, sprn); } + +void spr_write_MMCR0_ureg(DisasContext *ctx, int sprn, int gprn) +{ + spr_noaccess(ctx, gprn, sprn); +} #endif /* SPR common to all non-embedded PowerPC */