diff mbox series

[RESEND,3/6] hw/mips/gt64xxx: Fix typos in qemu_log_mask() formats

Message ID 20210309142630.728014-4-f4bug@amsat.org
State New
Headers show
Series hw/mips/gt64120: Minor fixes | expand

Commit Message

Philippe Mathieu-Daudé March 9, 2021, 2:26 p.m. UTC 
Fix the following typos:
- GT_PCI1_CFGDATA is not a timer register but a PCI one,
- zero-padding flag is out of the format

Fixes: 641ca2bfcd5 ("hw/mips/gt64xxx_pci: Use qemu_log_mask() instead of debug printf()")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 hw/mips/gt64xxx_pci.c | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

Comments

BALATON Zoltan March 9, 2021, 3:39 p.m. UTC | #1 
On Tue, 9 Mar 2021, Philippe Mathieu-Daudé wrote:

> Fix the following typos:
> - GT_PCI1_CFGDATA is not a timer register but a PCI one,
> - zero-padding flag is out of the format
>
> Fixes: 641ca2bfcd5 ("hw/mips/gt64xxx_pci: Use qemu_log_mask() instead of debug printf()")
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>

> ---
> hw/mips/gt64xxx_pci.c | 20 ++++++++++----------
> 1 file changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c
> index 99b1690af19..8ff31380d74 100644
> --- a/hw/mips/gt64xxx_pci.c
> +++ b/hw/mips/gt64xxx_pci.c
> @@ -463,7 +463,7 @@ static void gt64120_writel(void *opaque, hwaddr addr,
>         /* Read-only registers, do nothing */
>         qemu_log_mask(LOG_GUEST_ERROR,
>                       "gt64120: Read-only register write "
> -                      "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
> +                      "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
>                       saddr << 2, size, size << 1, val);
>         break;
>
> @@ -473,7 +473,7 @@ static void gt64120_writel(void *opaque, hwaddr addr,
>         /* Read-only registers, do nothing */
>         qemu_log_mask(LOG_GUEST_ERROR,
>                       "gt64120: Read-only register write "
> -                      "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
> +                      "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
>                       saddr << 2, size, size << 1, val);
>         break;
>
> @@ -515,7 +515,7 @@ static void gt64120_writel(void *opaque, hwaddr addr,
>         /* Not implemented */
>         qemu_log_mask(LOG_UNIMP,
>                       "gt64120: Unimplemented device register write "
> -                      "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
> +                      "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
>                       saddr << 2, size, size << 1, val);
>         break;
>
> @@ -528,7 +528,7 @@ static void gt64120_writel(void *opaque, hwaddr addr,
>         /* Read-only registers, do nothing */
>         qemu_log_mask(LOG_GUEST_ERROR,
>                       "gt64120: Read-only register write "
> -                      "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
> +                      "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
>                       saddr << 2, size, size << 1, val);
>         break;
>
> @@ -565,7 +565,7 @@ static void gt64120_writel(void *opaque, hwaddr addr,
>         /* Not implemented */
>         qemu_log_mask(LOG_UNIMP,
>                       "gt64120: Unimplemented DMA register write "
> -                      "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
> +                      "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
>                       saddr << 2, size, size << 1, val);
>         break;
>
> @@ -578,7 +578,7 @@ static void gt64120_writel(void *opaque, hwaddr addr,
>         /* Not implemented */
>         qemu_log_mask(LOG_UNIMP,
>                       "gt64120: Unimplemented timer register write "
> -                      "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
> +                      "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
>                       saddr << 2, size, size << 1, val);
>         break;
>
> @@ -621,8 +621,8 @@ static void gt64120_writel(void *opaque, hwaddr addr,
>     case GT_PCI1_CFGDATA:
>         /* not implemented */
>         qemu_log_mask(LOG_UNIMP,
> -                      "gt64120: Unimplemented timer register write "
> -                      "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
> +                      "gt64120: Unimplemented PCI register write "
> +                      "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
>                       saddr << 2, size, size << 1, val);
>         break;
>     case GT_PCI0_CFGADDR:
> @@ -682,7 +682,7 @@ static void gt64120_writel(void *opaque, hwaddr addr,
>     default:
>         qemu_log_mask(LOG_GUEST_ERROR,
>                       "gt64120: Illegal register write "
> -                      "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
> +                      "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
>                       saddr << 2, size, size << 1, val);
>         break;
>     }
> @@ -958,7 +958,7 @@ static uint64_t gt64120_readl(void *opaque,
>         val = s->regs[saddr];
>         qemu_log_mask(LOG_GUEST_ERROR,
>                       "gt64120: Illegal register read "
> -                      "reg:0x03%x size:%u value:0x%0*x\n",
> +                      "reg:0x%03x size:%u value:0x%0*x\n",
>                       saddr << 2, size, size << 1, val);
>         break;
>     }
>
diff mbox series

Patch

diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c
index 99b1690af19..8ff31380d74 100644
--- a/hw/mips/gt64xxx_pci.c
+++ b/hw/mips/gt64xxx_pci.c
@@ -463,7 +463,7 @@  static void gt64120_writel(void *opaque, hwaddr addr,
         /* Read-only registers, do nothing */
         qemu_log_mask(LOG_GUEST_ERROR,
                       "gt64120: Read-only register write "
-                      "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
+                      "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
                       saddr << 2, size, size << 1, val);
         break;
 
@@ -473,7 +473,7 @@  static void gt64120_writel(void *opaque, hwaddr addr,
         /* Read-only registers, do nothing */
         qemu_log_mask(LOG_GUEST_ERROR,
                       "gt64120: Read-only register write "
-                      "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
+                      "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
                       saddr << 2, size, size << 1, val);
         break;
 
@@ -515,7 +515,7 @@  static void gt64120_writel(void *opaque, hwaddr addr,
         /* Not implemented */
         qemu_log_mask(LOG_UNIMP,
                       "gt64120: Unimplemented device register write "
-                      "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
+                      "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
                       saddr << 2, size, size << 1, val);
         break;
 
@@ -528,7 +528,7 @@  static void gt64120_writel(void *opaque, hwaddr addr,
         /* Read-only registers, do nothing */
         qemu_log_mask(LOG_GUEST_ERROR,
                       "gt64120: Read-only register write "
-                      "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
+                      "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
                       saddr << 2, size, size << 1, val);
         break;
 
@@ -565,7 +565,7 @@  static void gt64120_writel(void *opaque, hwaddr addr,
         /* Not implemented */
         qemu_log_mask(LOG_UNIMP,
                       "gt64120: Unimplemented DMA register write "
-                      "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
+                      "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
                       saddr << 2, size, size << 1, val);
         break;
 
@@ -578,7 +578,7 @@  static void gt64120_writel(void *opaque, hwaddr addr,
         /* Not implemented */
         qemu_log_mask(LOG_UNIMP,
                       "gt64120: Unimplemented timer register write "
-                      "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
+                      "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
                       saddr << 2, size, size << 1, val);
         break;
 
@@ -621,8 +621,8 @@  static void gt64120_writel(void *opaque, hwaddr addr,
     case GT_PCI1_CFGDATA:
         /* not implemented */
         qemu_log_mask(LOG_UNIMP,
-                      "gt64120: Unimplemented timer register write "
-                      "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
+                      "gt64120: Unimplemented PCI register write "
+                      "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
                       saddr << 2, size, size << 1, val);
         break;
     case GT_PCI0_CFGADDR:
@@ -682,7 +682,7 @@  static void gt64120_writel(void *opaque, hwaddr addr,
     default:
         qemu_log_mask(LOG_GUEST_ERROR,
                       "gt64120: Illegal register write "
-                      "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
+                      "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
                       saddr << 2, size, size << 1, val);
         break;
     }
@@ -958,7 +958,7 @@  static uint64_t gt64120_readl(void *opaque,
         val = s->regs[saddr];
         qemu_log_mask(LOG_GUEST_ERROR,
                       "gt64120: Illegal register read "
-                      "reg:0x03%x size:%u value:0x%0*x\n",
+                      "reg:0x%03x size:%u value:0x%0*x\n",
                       saddr << 2, size, size << 1, val);
         break;
     }