Message ID | 20210309142630.728014-6-f4bug@amsat.org |
---|---|
State | New |
Headers | show |
Series | hw/mips/gt64120: Minor fixes | expand |
On Tue, 9 Mar 2021, Philippe Mathieu-Daudé wrote: > Trace all accesses to Internal Space Decode (ISD) registers. > > Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu> > --- > hw/mips/gt64xxx_pci.c | 2 ++ > hw/mips/trace-events | 2 ++ > 2 files changed, 4 insertions(+) > > diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c > index 9a12d00d1e1..43349d6837d 100644 > --- a/hw/mips/gt64xxx_pci.c > +++ b/hw/mips/gt64xxx_pci.c > @@ -387,6 +387,7 @@ static void gt64120_writel(void *opaque, hwaddr addr, > PCIHostState *phb = PCI_HOST_BRIDGE(s); > uint32_t saddr = addr >> 2; > > + trace_gt64120_write(addr, val); > if (!(s->regs[GT_CPU] & 0x00001000)) { > val = bswap32(val); > } > @@ -966,6 +967,7 @@ static uint64_t gt64120_readl(void *opaque, > if (!(s->regs[GT_CPU] & 0x00001000)) { > val = bswap32(val); > } > + trace_gt64120_read(addr, val); > > return val; > } > diff --git a/hw/mips/trace-events b/hw/mips/trace-events > index b7e934c3933..13ee731a488 100644 > --- a/hw/mips/trace-events > +++ b/hw/mips/trace-events > @@ -1,4 +1,6 @@ > # gt64xxx_pci.c > +gt64120_read(uint64_t addr, uint64_t value) "gt64120 read 0x%03"PRIx64" value:0x%08" PRIx64 > +gt64120_write(uint64_t addr, uint64_t value) "gt64120 write 0x%03"PRIx64" value:0x%08" PRIx64 > gt64120_read_intreg(const char *regname, unsigned size, uint64_t value) "gt64120 read %s size:%u value:0x%08" PRIx64 > gt64120_write_intreg(const char *regname, unsigned size, uint64_t value) "gt64120 write %s size:%u value:0x%08" PRIx64 > gt64120_isd_remap(uint64_t from_length, uint64_t from_addr, uint64_t to_length, uint64_t to_addr) "ISD: 0x%08" PRIx64 "@0x%08" PRIx64 " -> 0x%08" PRIx64 "@0x%08" PRIx64 >
On Tue, 9 Mar 2021, Philippe Mathieu-Daudé wrote: > Trace all accesses to Internal Space Decode (ISD) registers. > > Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > --- > hw/mips/gt64xxx_pci.c | 2 ++ > hw/mips/trace-events | 2 ++ > 2 files changed, 4 insertions(+) > > diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c > index 9a12d00d1e1..43349d6837d 100644 > --- a/hw/mips/gt64xxx_pci.c > +++ b/hw/mips/gt64xxx_pci.c > @@ -387,6 +387,7 @@ static void gt64120_writel(void *opaque, hwaddr addr, > PCIHostState *phb = PCI_HOST_BRIDGE(s); > uint32_t saddr = addr >> 2; > > + trace_gt64120_write(addr, val); > if (!(s->regs[GT_CPU] & 0x00001000)) { > val = bswap32(val); > } > @@ -966,6 +967,7 @@ static uint64_t gt64120_readl(void *opaque, > if (!(s->regs[GT_CPU] & 0x00001000)) { > val = bswap32(val); > } > + trace_gt64120_read(addr, val); There are a few other places where logs use saddr << 2 instead of addr so for consistency you might consider either changing those too or use saddr << 2 here as well. (Reviewed-by still stands either way.) Regards, BALATON Zoltan > > return val; > } > diff --git a/hw/mips/trace-events b/hw/mips/trace-events > index b7e934c3933..13ee731a488 100644 > --- a/hw/mips/trace-events > +++ b/hw/mips/trace-events > @@ -1,4 +1,6 @@ > # gt64xxx_pci.c > +gt64120_read(uint64_t addr, uint64_t value) "gt64120 read 0x%03"PRIx64" value:0x%08" PRIx64 > +gt64120_write(uint64_t addr, uint64_t value) "gt64120 write 0x%03"PRIx64" value:0x%08" PRIx64 > gt64120_read_intreg(const char *regname, unsigned size, uint64_t value) "gt64120 read %s size:%u value:0x%08" PRIx64 > gt64120_write_intreg(const char *regname, unsigned size, uint64_t value) "gt64120 write %s size:%u value:0x%08" PRIx64 > gt64120_isd_remap(uint64_t from_length, uint64_t from_addr, uint64_t to_length, uint64_t to_addr) "ISD: 0x%08" PRIx64 "@0x%08" PRIx64 " -> 0x%08" PRIx64 "@0x%08" PRIx64 >
diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index 9a12d00d1e1..43349d6837d 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -387,6 +387,7 @@ static void gt64120_writel(void *opaque, hwaddr addr, PCIHostState *phb = PCI_HOST_BRIDGE(s); uint32_t saddr = addr >> 2; + trace_gt64120_write(addr, val); if (!(s->regs[GT_CPU] & 0x00001000)) { val = bswap32(val); } @@ -966,6 +967,7 @@ static uint64_t gt64120_readl(void *opaque, if (!(s->regs[GT_CPU] & 0x00001000)) { val = bswap32(val); } + trace_gt64120_read(addr, val); return val; } diff --git a/hw/mips/trace-events b/hw/mips/trace-events index b7e934c3933..13ee731a488 100644 --- a/hw/mips/trace-events +++ b/hw/mips/trace-events @@ -1,4 +1,6 @@ # gt64xxx_pci.c +gt64120_read(uint64_t addr, uint64_t value) "gt64120 read 0x%03"PRIx64" value:0x%08" PRIx64 +gt64120_write(uint64_t addr, uint64_t value) "gt64120 write 0x%03"PRIx64" value:0x%08" PRIx64 gt64120_read_intreg(const char *regname, unsigned size, uint64_t value) "gt64120 read %s size:%u value:0x%08" PRIx64 gt64120_write_intreg(const char *regname, unsigned size, uint64_t value) "gt64120 write %s size:%u value:0x%08" PRIx64 gt64120_isd_remap(uint64_t from_length, uint64_t from_addr, uint64_t to_length, uint64_t to_addr) "ISD: 0x%08" PRIx64 "@0x%08" PRIx64 " -> 0x%08" PRIx64 "@0x%08" PRIx64
Trace all accesses to Internal Space Decode (ISD) registers. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> --- hw/mips/gt64xxx_pci.c | 2 ++ hw/mips/trace-events | 2 ++ 2 files changed, 4 insertions(+)