| Message ID | 20210309142630.728014-5-f4bug@amsat.org |
|---|---|
| State | New |
| Headers | show |
| Series | hw/mips/gt64120: Minor fixes | expand |
On Tue, 9 Mar 2021, Philippe Mathieu-Daudé wrote: > We want to trace all register accesses. First rename the current > gt64120_read / gt64120_write events with '_intreg' suffix, as they > are restricted to interrupt registers. > > Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu> > --- > hw/mips/gt64xxx_pci.c | 16 ++++++++-------- > hw/mips/trace-events | 4 ++-- > 2 files changed, 10 insertions(+), 10 deletions(-) > > diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c > index 8ff31380d74..9a12d00d1e1 100644 > --- a/hw/mips/gt64xxx_pci.c > +++ b/hw/mips/gt64xxx_pci.c > @@ -642,19 +642,19 @@ static void gt64120_writel(void *opaque, hwaddr addr, > /* not really implemented */ > s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe)); > s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe); > - trace_gt64120_write("INTRCAUSE", size, val); > + trace_gt64120_write_intreg("INTRCAUSE", size, val); > break; > case GT_INTRMASK: > s->regs[saddr] = val & 0x3c3ffffe; > - trace_gt64120_write("INTRMASK", size, val); > + trace_gt64120_write_intreg("INTRMASK", size, val); > break; > case GT_PCI0_ICMASK: > s->regs[saddr] = val & 0x03fffffe; > - trace_gt64120_write("ICMASK", size, val); > + trace_gt64120_write_intreg("ICMASK", size, val); > break; > case GT_PCI0_SERR0MASK: > s->regs[saddr] = val & 0x0000003f; > - trace_gt64120_write("SERR0MASK", size, val); > + trace_gt64120_write_intreg("SERR0MASK", size, val); > break; > > /* Reserved when only PCI_0 is configured. */ > @@ -929,19 +929,19 @@ static uint64_t gt64120_readl(void *opaque, > /* Interrupts */ > case GT_INTRCAUSE: > val = s->regs[saddr]; > - trace_gt64120_read("INTRCAUSE", size, val); > + trace_gt64120_read_intreg("INTRCAUSE", size, val); > break; > case GT_INTRMASK: > val = s->regs[saddr]; > - trace_gt64120_read("INTRMASK", size, val); > + trace_gt64120_read_intreg("INTRMASK", size, val); > break; > case GT_PCI0_ICMASK: > val = s->regs[saddr]; > - trace_gt64120_read("ICMASK", size, val); > + trace_gt64120_read_intreg("ICMASK", size, val); > break; > case GT_PCI0_SERR0MASK: > val = s->regs[saddr]; > - trace_gt64120_read("SERR0MASK", size, val); > + trace_gt64120_read_intreg("SERR0MASK", size, val); > break; > > /* Reserved when only PCI_0 is configured. */ > diff --git a/hw/mips/trace-events b/hw/mips/trace-events > index 915139d9811..b7e934c3933 100644 > --- a/hw/mips/trace-events > +++ b/hw/mips/trace-events > @@ -1,4 +1,4 @@ > # gt64xxx_pci.c > -gt64120_read(const char *regname, unsigned size, uint64_t value) "gt64120 read %s size:%u value:0x%08" PRIx64 > -gt64120_write(const char *regname, unsigned size, uint64_t value) "gt64120 write %s size:%u value:0x%08" PRIx64 > +gt64120_read_intreg(const char *regname, unsigned size, uint64_t value) "gt64120 read %s size:%u value:0x%08" PRIx64 > +gt64120_write_intreg(const char *regname, unsigned size, uint64_t value) "gt64120 write %s size:%u value:0x%08" PRIx64 > gt64120_isd_remap(uint64_t from_length, uint64_t from_addr, uint64_t to_length, uint64_t to_addr) "ISD: 0x%08" PRIx64 "@0x%08" PRIx64 " -> 0x%08" PRIx64 "@0x%08" PRIx64 >
diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index 8ff31380d74..9a12d00d1e1 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -642,19 +642,19 @@ static void gt64120_writel(void *opaque, hwaddr addr, /* not really implemented */ s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe)); s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe); - trace_gt64120_write("INTRCAUSE", size, val); + trace_gt64120_write_intreg("INTRCAUSE", size, val); break; case GT_INTRMASK: s->regs[saddr] = val & 0x3c3ffffe; - trace_gt64120_write("INTRMASK", size, val); + trace_gt64120_write_intreg("INTRMASK", size, val); break; case GT_PCI0_ICMASK: s->regs[saddr] = val & 0x03fffffe; - trace_gt64120_write("ICMASK", size, val); + trace_gt64120_write_intreg("ICMASK", size, val); break; case GT_PCI0_SERR0MASK: s->regs[saddr] = val & 0x0000003f; - trace_gt64120_write("SERR0MASK", size, val); + trace_gt64120_write_intreg("SERR0MASK", size, val); break; /* Reserved when only PCI_0 is configured. */ @@ -929,19 +929,19 @@ static uint64_t gt64120_readl(void *opaque, /* Interrupts */ case GT_INTRCAUSE: val = s->regs[saddr]; - trace_gt64120_read("INTRCAUSE", size, val); + trace_gt64120_read_intreg("INTRCAUSE", size, val); break; case GT_INTRMASK: val = s->regs[saddr]; - trace_gt64120_read("INTRMASK", size, val); + trace_gt64120_read_intreg("INTRMASK", size, val); break; case GT_PCI0_ICMASK: val = s->regs[saddr]; - trace_gt64120_read("ICMASK", size, val); + trace_gt64120_read_intreg("ICMASK", size, val); break; case GT_PCI0_SERR0MASK: val = s->regs[saddr]; - trace_gt64120_read("SERR0MASK", size, val); + trace_gt64120_read_intreg("SERR0MASK", size, val); break; /* Reserved when only PCI_0 is configured. */ diff --git a/hw/mips/trace-events b/hw/mips/trace-events index 915139d9811..b7e934c3933 100644 --- a/hw/mips/trace-events +++ b/hw/mips/trace-events @@ -1,4 +1,4 @@ # gt64xxx_pci.c -gt64120_read(const char *regname, unsigned size, uint64_t value) "gt64120 read %s size:%u value:0x%08" PRIx64 -gt64120_write(const char *regname, unsigned size, uint64_t value) "gt64120 write %s size:%u value:0x%08" PRIx64 +gt64120_read_intreg(const char *regname, unsigned size, uint64_t value) "gt64120 read %s size:%u value:0x%08" PRIx64 +gt64120_write_intreg(const char *regname, unsigned size, uint64_t value) "gt64120 write %s size:%u value:0x%08" PRIx64 gt64120_isd_remap(uint64_t from_length, uint64_t from_addr, uint64_t to_length, uint64_t to_addr) "ISD: 0x%08" PRIx64 "@0x%08" PRIx64 " -> 0x%08" PRIx64 "@0x%08" PRIx64
We want to trace all register accesses. First rename the current gt64120_read / gt64120_write events with '_intreg' suffix, as they are restricted to interrupt registers. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> --- hw/mips/gt64xxx_pci.c | 16 ++++++++-------- hw/mips/trace-events | 4 ++-- 2 files changed, 10 insertions(+), 10 deletions(-)