Message ID | 20201218060114.3591217-1-alistair.francis@wdc.com |
---|---|
State | New |
Headers | show |
On Fri, 18 Dec 2020 at 06:01, Alistair Francis <alistair.francis@wdc.com> wrote: > > The following changes since commit 75ee62ac606bfc9eb59310b9446df3434bf6e8c2: > > Merge remote-tracking branch 'remotes/ehabkost-gl/tags/x86-next-pull-request' into staging (2020-12-17 18:53:36 +0000) > > are available in the Git repository at: > > git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20201217-1 > > for you to fetch changes up to d31e970a01e7399b9cd43ec0dc00c857d968987e: > > riscv/opentitan: Update the OpenTitan memory layout (2020-12-17 21:56:44 -0800) > > ---------------------------------------------------------------- > A collection of RISC-V improvements: > - Improve the sifive_u DTB generation > - Add QSPI NOR flash to Microchip PFSoC > - Fix a bug in the Hypervisor HLVX/HLV/HSV instructions > - Fix some mstatus mask defines > - Ibex PLIC improvements > - OpenTitan memory layout update > - Initial steps towards support for 32-bit CPUs on 64-bit builds > > ---------------------------------------------------------------- Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/6.0 for any user-visible changes. -- PMM