| Message ID | 20190411100836.646-11-david@redhat.com |
|---|---|
| State | New |
| Headers | show |
| Series | s390x/tcg: Vector Instruction Support Part 2 | expand |
On 4/11/19 12:08 AM, David Hildenbrand wrote: > + es | logical ? 0 : MO_SIGN); Incorrect operator precedence. You need: es | (logical ? 0 : MO_SIGN) or logical ? es : es | MO_SIGN And perhaps cse this expression into a temporary and not replicate it between the two reads. Otherwise, Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
On 13.04.19 01:14, Richard Henderson wrote: > On 4/11/19 12:08 AM, David Hildenbrand wrote: >> + es | logical ? 0 : MO_SIGN); > > Incorrect operator precedence. You need: > > es | (logical ? 0 : MO_SIGN) > > or > > logical ? es : es | MO_SIGN > > And perhaps cse this expression into a temporary > and not replicate it between the two reads. > > Otherwise, > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > > > r~ > Thanks, good catch! I'll do it like this +static DisasJumpType op_vec(DisasContext *s, DisasOps *o) +{ + uint8_t es = get_field(s->fields, m3); + const uint8_t enr = NUM_VEC_ELEMENTS(es) / 2 - 1; + + if (es > ES_64) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + if (s->fields->op2 == 0xdb) { + es |= MO_SIGN; + } + + o->in1 = tcg_temp_new_i64(); + o->in2 = tcg_temp_new_i64(); + read_vec_element_i64(o->in1, get_field(s->fields, v1), enr, es); + read_vec_element_i64(o->in2, get_field(s->fields, v2), enr, es); + return DISAS_NEXT; +}
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def index 64459465c5..52e398f515 100644 --- a/target/s390x/insn-data.def +++ b/target/s390x/insn-data.def @@ -1074,6 +1074,10 @@ F(0xe7f0, VAVGL, VRR_c, V, 0, 0, 0, 0, vavgl, 0, IF_VEC) /* VECTOR CHECKSUM */ F(0xe766, VCKSM, VRR_c, V, 0, 0, 0, 0, vcksm, 0, IF_VEC) +/* VECTOR ELEMENT COMPARE */ + F(0xe7db, VEC, VRR_a, V, 0, 0, 0, 0, vec, cmps64, IF_VEC) +/* VECTOR ELEMENT COMPARE LOGICAL */ + F(0xe7d9, VECL, VRR_a, V, 0, 0, 0, 0, vec, cmpu64, IF_VEC) #ifndef CONFIG_USER_ONLY /* COMPARE AND SWAP AND PURGE */ diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c index 7a7e185d43..c7462d1bb1 100644 --- a/target/s390x/translate_vx.inc.c +++ b/target/s390x/translate_vx.inc.c @@ -1327,3 +1327,23 @@ static DisasJumpType op_vcksm(DisasContext *s, DisasOps *o) tcg_temp_free_i32(sum); return DISAS_NEXT; } + +static DisasJumpType op_vec(DisasContext *s, DisasOps *o) +{ + const uint8_t es = get_field(s->fields, m3); + const uint8_t enr = NUM_VEC_ELEMENTS(es) / 2 - 1; + const bool logical = s->fields->op2 == 0xd9; + + if (es > ES_64) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + o->in1 = tcg_temp_new_i64(); + o->in2 = tcg_temp_new_i64(); + read_vec_element_i64(o->in1, get_field(s->fields, v1), enr, + es | logical ? 0 : MO_SIGN); + read_vec_element_i64(o->in2, get_field(s->fields, v2), enr, + es | logical ? 0 : MO_SIGN); + return DISAS_NEXT; +}
Fairly easy to implement, we can make use of the existing CC helpers cmps64 and cmpu64 - we siply have to sign extend the elements. Signed-off-by: David Hildenbrand <david@redhat.com> --- target/s390x/insn-data.def | 4 ++++ target/s390x/translate_vx.inc.c | 20 ++++++++++++++++++++ 2 files changed, 24 insertions(+)