diff mbox series

[34/35] target/mips: Disable gdbstub nanoMIPS ISA bit

Message ID	20180620120620.12806-35-yongbok.kim@mips.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: Yongbok Kim <yongbok.kim@mips.com> To: <qemu-devel@nongnu.org> Date: Wed, 20 Jun 2018 13:06:19 +0100 Message-ID: <20180620120620.12806-35-yongbok.kim@mips.com> In-Reply-To: <20180620120620.12806-1-yongbok.kim@mips.com> References: <20180620120620.12806-1-yongbok.kim@mips.com> MIME-Version: 1.0 Content-Type: text/plain META: BESS Outbound Subject: [Qemu-devel] [PATCH 34/35] target/mips: Disable gdbstub nanoMIPS ISA bit Precedence: list Cc: Aleksandar.Markovic@mips.com, Paul.Burton@mips.com, Stefan.Markovic@mips.com, Matthew.Fortune@mips.com, James.Hogan@mips.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	nanoMIPS \| expand [00/35] nanoMIPS [01/35] target/mips: Raise a RI when given fs is n/a from CTC1 [02/35] target/mips: Fix microMIPS on reset [03/35] target/mips: Add nanoMIPS OPCODE table [04/35] target/mips: Add decode_nanomips_opc() [05/35] target/mips: Add nanoMIPS 16bit ld/st instructions [06/35] target/mips: Add nanoMIPS pool16c instructions [07/35] target/mips: Add nanoMIPS save and restore [08/35] target/mips: Add nanoMIPS 32bit instructions [09/35] target/mips: Add nanoMIPS 48bit instructions [10/35] target/mips: Add nanoMIPS pool32f instructions [11/35] target/mips: Add nanoMIPS pool32a0 instructions [12/35] target/mips: Add nanoMIPS pool32axf instructions [13/35] target/mips: Update gen_flt_ldst() [14/35] target/mips: Add nanoMIPS p_lsx instructions [15/35] target/mips: Implement nanoMIPS EXTW instruction [16/35] target/mips: Add has_isa_mode [17/35] target/mips: Add nanoMIPS load store instructions [18/35] target/mips: Add nanoMIPS branch instructions [19/35] target/mips: Implement nanoMIPS LLWP/SCWP pair [20/35] target/mips: Fix not to update BadVAddr in Debug Mode [21/35] target/mips: Add nanoMIPS rotx instruction [22/35] target/mips: Fix data type for offset [23/35] target/mips: Update BadInstr{P} regs on nanoMIPS [24/35] target/mips: Add nanoMIPS CP0_BadInstrX register [25/35] target/mips: Config3.ISAOnExc is read only in nanoMIPS [26/35] target/mips: Fix nanoMIPS exception_resume_pc [27/35] target/mips: Fix nanoMIPS set_hflags_for_handler [28/35] target/mips: Fix nanoMIPS set_pc [29/35] target/mips: Fix ERET/ERETNC can cause ADEL exception [30/35] hw/mips: Add basic nanoMIPS boot code [31/35] mips_malta: Setup GT64120 BARs in nanoMIPS bootloader [32/35] hw/mips: Fix semihosting argument passing for nanoMIPS bare metal [33/35] target/mips: Fix gdbstub to read/write 64 bit FP registers [34/35] target/mips: Disable gdbstub nanoMIPS ISA bit [35/35] target/mips: Add I7200 CPU

Commit Message

Yongbok Kim June 20, 2018, 12:06 p.m. UTC

From: James Hogan <james.hogan@imgtec.com>

nanoMIPS has no ISA bit in the PC, so remove the handling of the low bit
of the PC in the MIPS gdbstub for nanoMIPS. This prevents the PC being
read as e.g. 0xbfc00001, and prevents writing to the PC clearing
MIPS_HFLAG_M16.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
---
 target/mips/gdbstub.c | 13 ++++++++-----
 1 file changed, 8 insertions(+), 5 deletions(-)

diff mbox series

Patch

diff --git a/target/mips/gdbstub.c b/target/mips/gdbstub.c
index 18e0e6d..559b69f 100644
--- a/target/mips/gdbstub.c
+++ b/target/mips/gdbstub.c
@@ -60,7 +60,8 @@  int mips_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
         return gdb_get_regl(mem_buf, (int32_t)env->CP0_Cause);
     case 37:
         return gdb_get_regl(mem_buf, env->active_tc.PC |
-                                     !!(env->hflags & MIPS_HFLAG_M16));
+                                     (!(env->insn_flags & ISA_NANOMIPS32) &&
+                                      env->hflags & MIPS_HFLAG_M16));
     case 72:
         return gdb_get_regl(mem_buf, 0); /* fp */
     case 89:
@@ -131,10 +132,12 @@  int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
         break;
     case 37:
         env->active_tc.PC = tmp & ~(target_ulong)1;
-        if (tmp & 1) {
-            env->hflags |= MIPS_HFLAG_M16;
-        } else {
-            env->hflags &= ~(MIPS_HFLAG_M16);
+        if (!(env->insn_flags & ISA_NANOMIPS32)) {
+            if (tmp & 1) {
+                env->hflags |= MIPS_HFLAG_M16;
+            } else {
+                env->hflags &= ~(MIPS_HFLAG_M16);
+            }
         }
         break;
     case 72: /* fp, ignored */