diff mbox series

[09/35] target/mips: Add nanoMIPS 48bit instructions

Message ID 20180620120620.12806-10-yongbok.kim@mips.com
State New
Headers show
Series nanoMIPS | expand

Commit Message

Yongbok Kim June 20, 2018, 12:05 p.m. UTC 
Add nanoMIPS 48bit instructions

Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
---
 target/mips/translate.c | 66 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 66 insertions(+)

Comments

Richard Henderson June 24, 2018, 11:49 p.m. UTC | #1 
On 06/20/2018 05:05 AM, Yongbok Kim wrote:
>      case NM_P48I:
> +        insn = cpu_lduw_code(env, ctx->base.pc_next + 4);

Surely split this case out to a new function.  And properly form the common,
signed 32-bit offset once before the switch.

> +        switch ((ctx->opcode >> 16) & 0x1f) {
> +        case NM_LI48:
> +            if (rt != 0) {
> +                tcg_gen_movi_tl(cpu_gpr[rt],
> +                                extract32(ctx->opcode, 0, 16) | insn << 16);

The 32-bit constant is to be sign-extended for nanomips 64.

> +            }
> +            break;
> +        case NM_ADDIU48:
> +            if (rt != 0) {
> +                tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rt],
> +                                extract32(ctx->opcode, 0, 16) | insn << 16);

Likewise.

> +                tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
> +            }
> +            break;
> +        case NM_ADDIUGP48:
> +            if (rt != 0) {
> +                tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[28],
> +                                extract32(ctx->opcode, 0, 16) | insn << 16);

Likewise.

> +                tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);

Behaves-like DADDIU[GP48].  Which would indicate using gen_op_addr_add[i].

I know you're only targeting nanomips32 now, but I think you need to be clearer
about all of these 64-bit edge cases now, lest they be very difficult to pick
out later.

> +            }
> +            break;
> +        case NM_ADDIUPC48:
> +            if (rt != 0) {
> +                int32_t offset = extract32(ctx->opcode, 0, 16) | insn << 16;
> +                target_long addr = addr_add(ctx, ctx->base.pc_next + 6, offset);
> +
> +                tcg_gen_movi_tl(cpu_gpr[rt], addr);
> +                tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);

Likewise.  And the ext32s would be doubly redundant with that already done in
addr_add.


r~
diff mbox series

Patch

diff --git a/target/mips/translate.c b/target/mips/translate.c
index c9b46dd..f3a8845 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -16407,6 +16407,72 @@  static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
         }
         break;
     case NM_P48I:
+        insn = cpu_lduw_code(env, ctx->base.pc_next + 4);
+        switch ((ctx->opcode >> 16) & 0x1f) {
+        case NM_LI48:
+            if (rt != 0) {
+                tcg_gen_movi_tl(cpu_gpr[rt],
+                                extract32(ctx->opcode, 0, 16) | insn << 16);
+            }
+            break;
+        case NM_ADDIU48:
+            if (rt != 0) {
+                tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rt],
+                                extract32(ctx->opcode, 0, 16) | insn << 16);
+                tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
+            }
+            break;
+        case NM_ADDIUGP48:
+            if (rt != 0) {
+                tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[28],
+                                extract32(ctx->opcode, 0, 16) | insn << 16);
+                tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
+            }
+            break;
+        case NM_ADDIUPC48:
+            if (rt != 0) {
+                int32_t offset = extract32(ctx->opcode, 0, 16) | insn << 16;
+                target_long addr = addr_add(ctx, ctx->base.pc_next + 6, offset);
+
+                tcg_gen_movi_tl(cpu_gpr[rt], addr);
+                tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
+            }
+            break;
+        case NM_LWPC48:
+            if (rt != 0) {
+                TCGv t0;
+                t0 = tcg_temp_new();
+
+                int32_t offset = extract32(ctx->opcode, 0, 16) | insn << 16;
+                target_long addr = addr_add(ctx, ctx->base.pc_next + 6, offset);
+
+                tcg_gen_movi_tl(t0, addr);
+                tcg_gen_qemu_ld_tl(cpu_gpr[rt], t0, ctx->mem_idx, MO_TESL);
+                tcg_temp_free(t0);
+            }
+            break;
+        case NM_SWPC48:
+        {
+            TCGv t0, t1;
+            t0 = tcg_temp_new();
+            t1 = tcg_temp_new();
+
+            int32_t offset = extract32(ctx->opcode, 0, 16) | insn << 16;
+            target_long addr = addr_add(ctx, ctx->base.pc_next + 6, offset);
+
+            tcg_gen_movi_tl(t0, addr);
+            gen_load_gpr(t1, rt);
+
+            tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL);
+
+            tcg_temp_free(t0);
+            tcg_temp_free(t1);
+        }
+            break;
+        default:
+            generate_exception_end(ctx, EXCP_RI);
+            break;
+        }
         return 6;
     case NM_P_U12:
         switch ((ctx->opcode >> 12) & 0x0f) {