diff mbox series

[33/35] target/mips: Fix gdbstub to read/write 64 bit FP registers

Message ID 20180620120620.12806-34-yongbok.kim@mips.com
State New
Headers show
Series nanoMIPS | expand

Commit Message

Yongbok Kim June 20, 2018, 12:06 p.m. UTC 
From: Yongbok Kim <yongbok.kim@imgtec.com>

Fix gdbstub to read/write 64 bit FP registers

Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
---
 target/mips/gdbstub.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

Comments

Aleksandar Markovic June 22, 2018, 1:47 p.m. UTC | #1 
> From: Yongbok Kim <yongbok.kim@imgtec.com>
>
> Fix gdbstub to read/write 64 bit FP registers
>
> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>

Reviewed-by: Aleksandar Markovic <aleksandar.markovic@mips.com>

> ---
>  target/mips/gdbstub.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/target/mips/gdbstub.c b/target/mips/gdbstub.c
> index 6d1fb70..18e0e6d 100644
> --- a/target/mips/gdbstub.c
> +++ b/target/mips/gdbstub.c
> @@ -39,7 +39,7 @@ int mips_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
>              return gdb_get_regl(mem_buf, (int32_t)env->active_fpu.fcr0);
>          default:
>              if (env->CP0_Status & (1 << CP0St_FR)) {
> -                return gdb_get_regl(mem_buf,
> +                return gdb_get_reg64(mem_buf,
>                      env->active_fpu.fpr[n - 38].d);
>              } else {
>                  return gdb_get_regl(mem_buf,
> @@ -100,6 +100,7 @@ int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
>              break;
>          default:
>              if (env->CP0_Status & (1 << CP0St_FR)) {
> +                uint64_t tmp = ldq_p(mem_buf);
>                  env->active_fpu.fpr[n - 38].d = tmp;
>              } else {
>                  env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp;
> --
> 1.9.1
diff mbox series

Patch

diff --git a/target/mips/gdbstub.c b/target/mips/gdbstub.c
index 6d1fb70..18e0e6d 100644
--- a/target/mips/gdbstub.c
+++ b/target/mips/gdbstub.c
@@ -39,7 +39,7 @@  int mips_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
             return gdb_get_regl(mem_buf, (int32_t)env->active_fpu.fcr0);
         default:
             if (env->CP0_Status & (1 << CP0St_FR)) {
-                return gdb_get_regl(mem_buf,
+                return gdb_get_reg64(mem_buf,
                     env->active_fpu.fpr[n - 38].d);
             } else {
                 return gdb_get_regl(mem_buf,
@@ -100,6 +100,7 @@  int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
             break;
         default:
             if (env->CP0_Status & (1 << CP0St_FR)) {
+                uint64_t tmp = ldq_p(mem_buf);
                 env->active_fpu.fpr[n - 38].d = tmp;
             } else {
                 env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp;