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[PULL,22/27] elf: Define MIPS_ABI_FP_UNKNOWN macro

Message ID	1540826418-5501-23-git-send-email-aleksandar.markovic@rt-rk.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: Aleksandar Markovic <aleksandar.markovic@rt-rk.com> To: qemu-devel@nongnu.org Date: Mon, 29 Oct 2018 16:20:13 +0100 Message-Id: <1540826418-5501-23-git-send-email-aleksandar.markovic@rt-rk.com> In-Reply-To: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> Subject: [Qemu-devel] [PULL 22/27] elf: Define MIPS_ABI_FP_UNKNOWN macro Precedence: list Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	[PULL,01/27] target/mips: Add two missing breaks for NM_LLWPE and NM_SCWPE decoder cases \| expand [PULL,01/27] target/mips: Add two missing breaks for NM_LLWPE and NM_SCWPE decoder cases [PULL,02/27] target/mips: Introduce MXU registers [PULL,03/27] target/mips: Define a bit for MXU in insn_flags [PULL,04/27] target/mips: Amend MXU instruction opcodes [PULL,05/27] target/mips: Add and integrate MXU decoding engine placeholder [PULL,06/27] target/mips: Add MXU decoding engine [PULL,07/27] target/mips: Add bit encoding for MXU accumulate add/sub 1-bit pattern 'aptn1' [PULL,08/27] target/mips: Add bit encoding for MXU accumulate add/sub 2-bit pattern 'aptn2' [PULL,09/27] target/mips: Add bit encoding for MXU execute add/sub pattern 'eptn2' [PULL,10/27] target/mips: Add bit encoding for MXU operand getting pattern 'optn2' [PULL,11/27] target/mips: Add bit encoding for MXU operand getting pattern 'optn3' [PULL,12/27] target/mips: Add emulation of non-MXU MULL within MXU decoding engine [PULL,13/27] target/mips: Add emulation of MXU instructions S32I2M and S32M2I [PULL,14/27] target/mips: Move MUL, S32M2I, S32I2M handling out of main MXU switch [PULL,15/27] target/mips: Add emulation of MXU instruction S8LDD [PULL,16/27] target/mips: Add emulation of MXU instruction D16MUL [PULL,17/27] target/mips: Add emulation of MXU instruction D16MAC [PULL,18/27] target/mips: Add emulation of MXU instructions Q8MUL and Q8MULSU [PULL,19/27] target/mips: Add emulation of MXU instructions S32LDD and S32LDDR [PULL,20/27] target/mips: Move MXU_EN check one level higher [PULL,21/27] target/mips: Amend MXU ASE overview note [PULL,22/27] elf: Define MIPS_ABI_FP_UNKNOWN macro [PULL,23/27] linux-user: Extend image_info struct with MIPS fp_abi and interp_fp_abi fields [PULL,24/27] linux-user: Extract MIPS abiflags from ELF file [PULL,25/27] linux-user: Read and set FP ABI value from MIPS abiflags [PULL,26/27] linux-user: Determine the desired FPU mode from MIPS.abiflags [PULL,27/27] linux-user: Add prctl() PR_SET_FP_MODE and PR_GET_FP_MODE implementations

Commit Message

Aleksandar Markovic Oct. 29, 2018, 3:20 p.m. UTC

From: Stefan Markovic <smarkovic@wavecomp.com>

Add MIPS_ABI_FP_UNKNOWN as QEMU internal value to represent
unknown fp_abi (based on kernel mips/include/asm/elf.h definition)

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
 include/elf.h | 2 ++
 1 file changed, 2 insertions(+)

diff mbox series

Patch

diff --git a/include/elf.h b/include/elf.h
index 5f45f9b..c151164 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -87,6 +87,8 @@  typedef int64_t  Elf64_Sxword;
 #define EF_MIPS_MACH_LS3A     0x00a20000  /* ST Microelectronics Loongson 3A */
 #define EF_MIPS_MACH          0x00ff0000  /* EF_MIPS_MACH_xxx selection mask */
 
+#define MIPS_ABI_FP_UNKNOWN   (-1)        /* Unknown FP ABI (internal)       */
+
 #define MIPS_ABI_FP_ANY       0x0         /* FP ABI doesn't matter           */
 #define MIPS_ABI_FP_DOUBLE    0x1         /* -mdouble-float                  */
 #define MIPS_ABI_FP_SINGLE    0x2         /* -msingle-float                  */