From patchwork Mon Oct 29 15:19:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 990308 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42kJSc1f3Qz9s55 for ; Tue, 30 Oct 2018 02:30:08 +1100 (AEDT) Received: from localhost ([::1]:46262 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9UT-0000lx-G7 for incoming@patchwork.ozlabs.org; Mon, 29 Oct 2018 11:30:05 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34202) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9LR-0008JG-IW for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:20:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gH9LJ-0003GG-Bd for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:20:43 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:38693 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gH9LJ-0003Cv-0Y for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:20:37 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 09D1F1A23BF; Mon, 29 Oct 2018 16:20:25 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id CD3F41A229A; Mon, 29 Oct 2018 16:20:24 +0100 (CET) From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Mon, 29 Oct 2018 16:19:52 +0100 Message-Id: <1540826418-5501-2-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL 01/27] target/mips: Add two missing breaks for NM_LLWPE and NM_SCWPE decoder cases X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Aleksandar Markovic Coverity found two fallthroughs that miss break statement. Fix them. Revieved-by: Stefan Markovic Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index 51a5488..3bdefc0 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -21321,6 +21321,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) check_eva(ctx); check_cp0_enabled(ctx); gen_llwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5)); + break; default: generate_exception_end(ctx, EXCP_RI); break; @@ -21339,6 +21340,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) check_eva(ctx); check_cp0_enabled(ctx); gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5)); + break; default: generate_exception_end(ctx, EXCP_RI); break; From patchwork Mon Oct 29 15:19:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 990317 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42kJcs1rxQz9s3Z for ; Tue, 30 Oct 2018 02:37:17 +1100 (AEDT) Received: from localhost ([::1]:46301 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9bL-0006E4-OA for incoming@patchwork.ozlabs.org; Mon, 29 Oct 2018 11:37:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34161) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9LN-0008Fp-SD for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:20:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gH9LI-0003Fl-VS for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:20:41 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:38701 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gH9LH-0003Cy-GL for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:20:36 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 0E8EC1A23CC; Mon, 29 Oct 2018 16:20:25 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id D58CA1A22CF; Mon, 29 Oct 2018 16:20:24 +0100 (CET) From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Mon, 29 Oct 2018 16:19:53 +0100 Message-Id: <1540826418-5501-3-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL 02/27] target/mips: Introduce MXU registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Craig Janeczek Define and initialize the 16 MXU registers - 15 general computational register, and 1 control register). There is also a zero register, but it does not have any corresponding variable. Reviewed-by: Richard Henderson Signed-off-by: Craig Janeczek Signed-off-by: Aleksandar Markovic --- target/mips/cpu.h | 10 ++++++++++ target/mips/translate.c | 20 ++++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index e48be4b..03c03fd 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -170,6 +170,16 @@ struct TCState { MSACSR_FS_MASK) float_status msa_fp_status; + +#define NUMBER_OF_MXU_REGISTERS 16 + target_ulong mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1]; + target_ulong mxu_cr; +#define MXU_CR_LC 31 +#define MXU_CR_RC 30 +#define MXU_CR_BIAS 2 +#define MXU_CR_RD_EN 1 +#define MXU_CR_MXU_EN 0 + }; typedef struct CPUMIPSState CPUMIPSState; diff --git a/target/mips/translate.c b/target/mips/translate.c index 3bdefc0..d6e733f 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -2379,6 +2379,10 @@ static TCGv_i32 fpu_fcr0, fpu_fcr31; static TCGv_i64 fpu_f64[32]; static TCGv_i64 msa_wr_d[64]; +/* MXU registers */ +static TCGv mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1]; +static TCGv mxu_CR; + #include "exec/gen-icount.h" #define gen_helper_0e0i(name, arg) do { \ @@ -2501,6 +2505,11 @@ static const char * const msaregnames[] = { "w30.d0", "w30.d1", "w31.d0", "w31.d1", }; +static const char * const mxuregnames[] = { + "XR1", "XR2", "XR3", "XR4", "XR5", "XR6", "XR7", "XR8", + "XR9", "XR10", "XR11", "XR12", "XR13", "XR14", "XR15", "MXU_CR", +}; + #define LOG_DISAS(...) \ do { \ if (MIPS_DEBUG_DISAS) { \ @@ -27231,6 +27240,17 @@ void mips_tcg_init(void) fpu_fcr31 = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMIPSState, active_fpu.fcr31), "fcr31"); + + for (i = 0; i < NUMBER_OF_MXU_REGISTERS - 1; i++) { + mxu_gpr[i] = tcg_global_mem_new(cpu_env, + offsetof(CPUMIPSState, + active_tc.mxu_gpr[i]), + mxuregnames[i]); + } + + mxu_CR = tcg_global_mem_new(cpu_env, + offsetof(CPUMIPSState, active_tc.mxu_cr), + mxuregnames[NUMBER_OF_MXU_REGISTERS - 1]); } #include "translate_init.inc.c" From patchwork Mon Oct 29 15:19:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 990316 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42kJc4493sz9s55 for ; Tue, 30 Oct 2018 02:36:36 +1100 (AEDT) Received: from localhost ([::1]:46298 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9ak-0005k4-0z for incoming@patchwork.ozlabs.org; Mon, 29 Oct 2018 11:36:34 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34201) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9LR-0008JF-IW for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:20:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gH9LJ-0003Gm-KR for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:20:43 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:38719 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gH9LJ-0003D7-5N for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:20:37 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 1BD131A229A; Mon, 29 Oct 2018 16:20:25 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id DFF1A1A22D6; Mon, 29 Oct 2018 16:20:24 +0100 (CET) From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Mon, 29 Oct 2018 16:19:54 +0100 Message-Id: <1540826418-5501-4-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL 03/27] target/mips: Define a bit for MXU in insn_flags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Craig Janeczek Define a bit for MXU in insn_flags. This is the first non-MIPS (third party) ASE supported in QEMU for MIPS, so it is placed in the section "bits 56-63: vendor-specific ASEs". Reviewed-by: Aleksandar Markovic Signed-off-by: Craig Janeczek Signed-off-by: Aleksandar Markovic --- target/mips/mips-defs.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index 5177618..dbdb4b2 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -69,6 +69,7 @@ * bits 56-63: vendor-specific ASEs */ #define ASE_MMI 0x0100000000000000ULL +#define ASE_MXU 0x0200000000000000ULL /* MIPS CPU defines. */ #define CPU_MIPS1 (ISA_MIPS1) From patchwork Mon Oct 29 15:19:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 990346 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42kK2Q3Zkhz9s3Z for ; Tue, 30 Oct 2018 02:55:57 +1100 (AEDT) Received: from localhost ([::1]:46408 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9tR-0001nU-68 for incoming@patchwork.ozlabs.org; Mon, 29 Oct 2018 11:55:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34399) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9Lg-0008Sp-Dz for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:21:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gH9Lb-0003PY-US for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:21:00 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:39357 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gH9Lb-0003GS-Bb for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:20:55 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 348101A23A4; Mon, 29 Oct 2018 16:20:25 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id E94381A23B5; Mon, 29 Oct 2018 16:20:24 +0100 (CET) From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Mon, 29 Oct 2018 16:19:55 +0100 Message-Id: <1540826418-5501-5-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL 04/27] target/mips: Amend MXU instruction opcodes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Aleksandar Markovic Amend MXU instruction opcodes. Pool04 is actually only instruction OPC_MXU_S16MAD. Two cases within S16MAD are recognized by 1-bit subfield 'aptn1'. Reviewed-by: Stefan Markovic Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 160 +++++++++++++++++++++--------------------------- 1 file changed, 69 insertions(+), 91 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index d6e733f..2335721 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1486,7 +1486,7 @@ enum { * S32OR XRa, XRb, XRc D32SARW XRa, XRb, XRc, Rb * Q16SLL XRa, XRb, XRc, XRd, sft4 * Q16SLR XRa, XRb, XRc, XRd, sft4 - * Miscelaneous instructions Q16SAR XRa, XRb, XRc, XRd, sft4 + * Miscellaneous instructions Q16SAR XRa, XRb, XRc, XRd, sft4 * ------------------------- Q16SLLV XRa, XRb, Rb * Q16SLRV XRa, XRb, Rb * S32SFL XRa, XRb, XRc, XRd, optn2 Q16SARV XRa, XRb, Rb @@ -1504,7 +1504,8 @@ enum { * * ┌─ 000000 ─ OPC_MXU_S32MADD * ├─ 000001 ─ OPC_MXU_S32MADDU - * ├─ 000010 ─ + * ├─ 000010 ─ (non-MXU OPC_MUL) + * │ * │ 20..18 * ├─ 000011 ─ OPC_MXU__POOL00 ─┬─ 000 ─ OPC_MXU_S32MAX * │ ├─ 001 ─ OPC_MXU_S32MIN @@ -1536,73 +1537,67 @@ enum { * ├─ 001010 ─ OPC_MXU_D16MAC * ├─ 001011 ─ OPC_MXU_D16MACF * ├─ 001100 ─ OPC_MXU_D16MADL - * │ 25..24 - * ├─ 001101 ─ OPC_MXU__POOL04 ─┬─ 00 ─ OPC_MXU_S16MAD - * │ └─ 01 ─ OPC_MXU_S16MAD_1 + * ├─ 001101 ─ OPC_MXU_S16MAD * ├─ 001110 ─ OPC_MXU_Q16ADD - * ├─ 001111 ─ OPC_MXU_D16MACE - * │ 23 - * ├─ 010000 ─ OPC_MXU__POOL05 ─┬─ 0 ─ OPC_MXU_S32LDD - * │ └─ 1 ─ OPC_MXU_S32LDDR + * ├─ 001111 ─ OPC_MXU_D16MACE 23 + * │ ┌─ 0 ─ OPC_MXU_S32LDD + * ├─ 010000 ─ OPC_MXU__POOL04 ─┴─ 1 ─ OPC_MXU_S32LDDR * │ * │ 23 - * ├─ 010001 ─ OPC_MXU__POOL06 ─┬─ 0 ─ OPC_MXU_S32STD + * ├─ 010001 ─ OPC_MXU__POOL05 ─┬─ 0 ─ OPC_MXU_S32STD * │ └─ 1 ─ OPC_MXU_S32STDR * │ * │ 13..10 - * ├─ 010010 ─ OPC_MXU__POOL07 ─┬─ 0000 ─ OPC_MXU_S32LDDV + * ├─ 010010 ─ OPC_MXU__POOL06 ─┬─ 0000 ─ OPC_MXU_S32LDDV * │ └─ 0001 ─ OPC_MXU_S32LDDVR * │ * │ 13..10 - * ├─ 010011 ─ OPC_MXU__POOL08 ─┬─ 0000 ─ OPC_MXU_S32STDV + * ├─ 010011 ─ OPC_MXU__POOL07 ─┬─ 0000 ─ OPC_MXU_S32STDV * │ └─ 0001 ─ OPC_MXU_S32STDVR * │ * │ 23 - * ├─ 010100 ─ OPC_MXU__POOL09 ─┬─ 0 ─ OPC_MXU_S32LDI + * ├─ 010100 ─ OPC_MXU__POOL08 ─┬─ 0 ─ OPC_MXU_S32LDI * │ └─ 1 ─ OPC_MXU_S32LDIR * │ * │ 23 - * ├─ 010101 ─ OPC_MXU__POOL10 ─┬─ 0 ─ OPC_MXU_S32SDI + * ├─ 010101 ─ OPC_MXU__POOL09 ─┬─ 0 ─ OPC_MXU_S32SDI * │ └─ 1 ─ OPC_MXU_S32SDIR * │ * │ 13..10 - * ├─ 010110 ─ OPC_MXU__POOL11 ─┬─ 0000 ─ OPC_MXU_S32LDIV + * ├─ 010110 ─ OPC_MXU__POOL10 ─┬─ 0000 ─ OPC_MXU_S32LDIV * │ └─ 0001 ─ OPC_MXU_S32LDIVR * │ * │ 13..10 - * ├─ 010111 ─ OPC_MXU__POOL12 ─┬─ 0000 ─ OPC_MXU_S32SDIV + * ├─ 010111 ─ OPC_MXU__POOL11 ─┬─ 0000 ─ OPC_MXU_S32SDIV * │ └─ 0001 ─ OPC_MXU_S32SDIVR * ├─ 011000 ─ OPC_MXU_D32ADD * │ 23..22 - * MXU ├─ 011001 ─ OPC_MXU__POOL13 ─┬─ 00 ─ OPC_MXU_D32ACC + * MXU ├─ 011001 ─ OPC_MXU__POOL12 ─┬─ 00 ─ OPC_MXU_D32ACC * opcodes ─┤ ├─ 01 ─ OPC_MXU_D32ACCM * │ └─ 10 ─ OPC_MXU_D32ASUM * ├─ 011010 ─ * │ 23..22 - * ├─ 011011 ─ OPC_MXU__POOL14 ─┬─ 00 ─ OPC_MXU_Q16ACC + * ├─ 011011 ─ OPC_MXU__POOL13 ─┬─ 00 ─ OPC_MXU_Q16ACC * │ ├─ 01 ─ OPC_MXU_Q16ACCM * │ └─ 10 ─ OPC_MXU_Q16ASUM * │ * │ 23..22 - * ├─ 011100 ─ OPC_MXU__POOL15 ─┬─ 00 ─ OPC_MXU_Q8ADDE + * ├─ 011100 ─ OPC_MXU__POOL14 ─┬─ 00 ─ OPC_MXU_Q8ADDE * │ ├─ 01 ─ OPC_MXU_D8SUM * ├─ 011101 ─ OPC_MXU_Q8ACCE └─ 10 ─ OPC_MXU_D8SUMC * ├─ 011110 ─ * ├─ 011111 ─ - * ├─ 100000 ─ - * ├─ 100001 ─ + * ├─ 100000 ─ (overlaps with CLZ) + * ├─ 100001 ─ (overlaps with CLO) * ├─ 100010 ─ OPC_MXU_S8LDD - * ├─ 100011 ─ OPC_MXU_S8STD - * ├─ 100100 ─ OPC_MXU_S8LDI - * ├─ 100101 ─ OPC_MXU_S8SDI - * │ 15..14 - * ├─ 100110 ─ OPC_MXU__POOL16 ─┬─ 00 ─ OPC_MXU_S32MUL - * │ ├─ 00 ─ OPC_MXU_S32MULU + * ├─ 100011 ─ OPC_MXU_S8STD 15..14 + * ├─ 100100 ─ OPC_MXU_S8LDI ┌─ 00 ─ OPC_MXU_S32MUL + * ├─ 100101 ─ OPC_MXU_S8SDI ├─ 00 ─ OPC_MXU_S32MULU * │ ├─ 00 ─ OPC_MXU_S32EXTR - * │ └─ 00 ─ OPC_MXU_S32EXTRV + * ├─ 100110 ─ OPC_MXU__POOL15 ─┴─ 00 ─ OPC_MXU_S32EXTRV * │ * │ 20..18 - * ├─ 100111 ─ OPC_MXU__POOL17 ─┬─ 000 ─ OPC_MXU_D32SARW + * ├─ 100111 ─ OPC_MXU__POOL16 ─┬─ 000 ─ OPC_MXU_D32SARW * │ ├─ 001 ─ OPC_MXU_S32ALN * ├─ 101000 ─ OPC_MXU_LXB ├─ 010 ─ OPC_MXU_S32ALNI * ├─ 101001 ─ ├─ 011 ─ OPC_MXU_S32NOR @@ -1610,33 +1605,24 @@ enum { * ├─ 101011 ─ OPC_MXU_S16STD ├─ 101 ─ OPC_MXU_S32OR * ├─ 101100 ─ OPC_MXU_S16LDI ├─ 110 ─ OPC_MXU_S32XOR * ├─ 101101 ─ OPC_MXU_S16SDI └─ 111 ─ OPC_MXU_S32LUI - * ├─ 101000 ─ - * ├─ 101001 ─ - * ├─ 101010 ─ - * ├─ 101011 ─ - * ├─ 101100 ─ - * ├─ 101101 ─ * ├─ 101110 ─ OPC_MXU_S32M2I * ├─ 101111 ─ OPC_MXU_S32I2M * ├─ 110000 ─ OPC_MXU_D32SLL - * ├─ 110001 ─ OPC_MXU_D32SLR - * ├─ 110010 ─ OPC_MXU_D32SARL - * ├─ 110011 ─ OPC_MXU_D32SAR - * ├─ 110100 ─ OPC_MXU_Q16SLL - * ├─ 110101 ─ OPC_MXU_Q16SLR 20..18 - * ├─ 110110 ─ OPC_MXU__POOL18 ─┬─ 000 ─ OPC_MXU_D32SLLV - * │ ├─ 001 ─ OPC_MXU_D32SLRV - * │ ├─ 010 ─ OPC_MXU_D32SARV - * │ ├─ 011 ─ OPC_MXU_Q16SLLV + * ├─ 110001 ─ OPC_MXU_D32SLR 20..18 + * ├─ 110010 ─ OPC_MXU_D32SARL ┌─ 000 ─ OPC_MXU_D32SLLV + * ├─ 110011 ─ OPC_MXU_D32SAR ├─ 001 ─ OPC_MXU_D32SLRV + * ├─ 110100 ─ OPC_MXU_Q16SLL ├─ 010 ─ OPC_MXU_D32SARV + * ├─ 110101 ─ OPC_MXU_Q16SLR ├─ 011 ─ OPC_MXU_Q16SLLV * │ ├─ 100 ─ OPC_MXU_Q16SLRV - * │ └─ 101 ─ OPC_MXU_Q16SARV + * ├─ 110110 ─ OPC_MXU__POOL17 ─┴─ 101 ─ OPC_MXU_Q16SARV + * │ * ├─ 110111 ─ OPC_MXU_Q16SAR * │ 23..22 - * ├─ 111000 ─ OPC_MXU__POOL19 ─┬─ 00 ─ OPC_MXU_Q8MUL + * ├─ 111000 ─ OPC_MXU__POOL18 ─┬─ 00 ─ OPC_MXU_Q8MUL * │ └─ 01 ─ OPC_MXU_Q8MULSU * │ * │ 20..18 - * ├─ 111001 ─ OPC_MXU__POOL20 ─┬─ 000 ─ OPC_MXU_Q8MOVZ + * ├─ 111001 ─ OPC_MXU__POOL19 ─┬─ 000 ─ OPC_MXU_Q8MOVZ * │ ├─ 001 ─ OPC_MXU_Q8MOVN * │ ├─ 010 ─ OPC_MXU_D16MOVZ * │ ├─ 011 ─ OPC_MXU_D16MOVN @@ -1644,13 +1630,13 @@ enum { * │ └─ 101 ─ OPC_MXU_S32MOV * │ * │ 23..22 - * ├─ 111010 ─ OPC_MXU__POOL21 ─┬─ 00 ─ OPC_MXU_Q8MAC + * ├─ 111010 ─ OPC_MXU__POOL20 ─┬─ 00 ─ OPC_MXU_Q8MAC * │ └─ 10 ─ OPC_MXU_Q8MACSU * ├─ 111011 ─ OPC_MXU_Q16SCOP * ├─ 111100 ─ OPC_MXU_Q8MADL * ├─ 111101 ─ OPC_MXU_S32SFL * ├─ 111110 ─ OPC_MXU_Q8SAD - * └─ 111111 ─ + * └─ 111111 ─ (overlaps with SDBBP) * * * Compiled after: @@ -1673,22 +1659,22 @@ enum { OPC_MXU_D16MAC = 0x0A, OPC_MXU_D16MACF = 0x0B, OPC_MXU_D16MADL = 0x0C, - OPC_MXU__POOL04 = 0x0D, + OPC_MXU_S16MAD = 0x0D, OPC_MXU_Q16ADD = 0x0E, OPC_MXU_D16MACE = 0x0F, - OPC_MXU__POOL05 = 0x10, - OPC_MXU__POOL06 = 0x11, - OPC_MXU__POOL07 = 0x12, - OPC_MXU__POOL08 = 0x13, - OPC_MXU__POOL09 = 0x14, - OPC_MXU__POOL10 = 0x15, - OPC_MXU__POOL11 = 0x16, - OPC_MXU__POOL12 = 0x17, + OPC_MXU__POOL04 = 0x10, + OPC_MXU__POOL05 = 0x11, + OPC_MXU__POOL06 = 0x12, + OPC_MXU__POOL07 = 0x13, + OPC_MXU__POOL08 = 0x14, + OPC_MXU__POOL09 = 0x15, + OPC_MXU__POOL10 = 0x16, + OPC_MXU__POOL11 = 0x17, OPC_MXU_D32ADD = 0x18, - OPC_MXU__POOL13 = 0x19, + OPC_MXU__POOL12 = 0x19, /* not assigned 0x1A */ - OPC_MXU__POOL14 = 0x1B, - OPC_MXU__POOL15 = 0x1C, + OPC_MXU__POOL13 = 0x1B, + OPC_MXU__POOL14 = 0x1C, OPC_MXU_Q8ACCE = 0x1D, /* not assigned 0x1E */ /* not assigned 0x1F */ @@ -1698,8 +1684,8 @@ enum { OPC_MXU_S8STD = 0x23, OPC_MXU_S8LDI = 0x24, OPC_MXU_S8SDI = 0x25, - OPC_MXU__POOL16 = 0x26, - OPC_MXU__POOL17 = 0x27, + OPC_MXU__POOL15 = 0x26, + OPC_MXU__POOL16 = 0x27, OPC_MXU_LXB = 0x28, /* not assigned 0x29 */ OPC_MXU_S16LDD = 0x2A, @@ -1714,11 +1700,11 @@ enum { OPC_MXU_D32SAR = 0x33, OPC_MXU_Q16SLL = 0x34, OPC_MXU_Q16SLR = 0x35, - OPC_MXU__POOL18 = 0x36, + OPC_MXU__POOL17 = 0x36, OPC_MXU_Q16SAR = 0x37, - OPC_MXU__POOL19 = 0x38, - OPC_MXU__POOL20 = 0x39, - OPC_MXU__POOL21 = 0x3A, + OPC_MXU__POOL18 = 0x38, + OPC_MXU__POOL19 = 0x39, + OPC_MXU__POOL20 = 0x3A, OPC_MXU_Q16SCOP = 0x3B, OPC_MXU_Q8MADL = 0x3C, OPC_MXU_S32SFL = 0x3D, @@ -1776,20 +1762,12 @@ enum { * MXU pool 04 */ enum { - OPC_MXU_S16MAD = 0x00, - OPC_MXU_S16MAD_1 = 0x01, -}; - -/* - * MXU pool 05 - */ -enum { OPC_MXU_S32LDD = 0x00, OPC_MXU_S32LDDR = 0x01, }; /* - * MXU pool 06 + * MXU pool 05 */ enum { OPC_MXU_S32STD = 0x00, @@ -1797,7 +1775,7 @@ enum { }; /* - * MXU pool 07 + * MXU pool 06 */ enum { OPC_MXU_S32LDDV = 0x00, @@ -1805,7 +1783,7 @@ enum { }; /* - * MXU pool 08 + * MXU pool 07 */ enum { OPC_MXU_S32STDV = 0x00, @@ -1813,7 +1791,7 @@ enum { }; /* - * MXU pool 09 + * MXU pool 08 */ enum { OPC_MXU_S32LDI = 0x00, @@ -1821,7 +1799,7 @@ enum { }; /* - * MXU pool 10 + * MXU pool 09 */ enum { OPC_MXU_S32SDI = 0x00, @@ -1829,7 +1807,7 @@ enum { }; /* - * MXU pool 11 + * MXU pool 10 */ enum { OPC_MXU_S32LDIV = 0x00, @@ -1837,7 +1815,7 @@ enum { }; /* - * MXU pool 12 + * MXU pool 11 */ enum { OPC_MXU_S32SDIV = 0x00, @@ -1845,7 +1823,7 @@ enum { }; /* - * MXU pool 13 + * MXU pool 12 */ enum { OPC_MXU_D32ACC = 0x00, @@ -1854,7 +1832,7 @@ enum { }; /* - * MXU pool 14 + * MXU pool 13 */ enum { OPC_MXU_Q16ACC = 0x00, @@ -1863,7 +1841,7 @@ enum { }; /* - * MXU pool 15 + * MXU pool 14 */ enum { OPC_MXU_Q8ADDE = 0x00, @@ -1872,7 +1850,7 @@ enum { }; /* - * MXU pool 16 + * MXU pool 15 */ enum { OPC_MXU_S32MUL = 0x00, @@ -1882,7 +1860,7 @@ enum { }; /* - * MXU pool 17 + * MXU pool 16 */ enum { OPC_MXU_D32SARW = 0x00, @@ -1896,7 +1874,7 @@ enum { }; /* - * MXU pool 18 + * MXU pool 17 */ enum { OPC_MXU_D32SLLV = 0x00, @@ -1908,7 +1886,7 @@ enum { }; /* - * MXU pool 19 + * MXU pool 18 */ enum { OPC_MXU_Q8MUL = 0x00, @@ -1916,7 +1894,7 @@ enum { }; /* - * MXU pool 20 + * MXU pool 19 */ enum { OPC_MXU_Q8MOVZ = 0x00, @@ -1928,7 +1906,7 @@ enum { }; /* - * MXU pool 21 + * MXU pool 20 */ enum { OPC_MXU_Q8MAC = 0x00, From patchwork Mon Oct 29 15:19:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 990303 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42kJNC52hNz9s55 for ; Tue, 30 Oct 2018 02:26:19 +1100 (AEDT) Received: from localhost ([::1]:46244 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9Ql-00047G-JV for incoming@patchwork.ozlabs.org; Mon, 29 Oct 2018 11:26:15 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34208) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9LR-0008JL-Io for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:20:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gH9LI-0003Ff-UO for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:20:43 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:38735 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gH9LH-0003DE-GM for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:20:36 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 312591A22D6; Mon, 29 Oct 2018 16:20:25 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 0DBE11A23C6; Mon, 29 Oct 2018 16:20:25 +0100 (CET) From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Mon, 29 Oct 2018 16:19:56 +0100 Message-Id: <1540826418-5501-6-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL 05/27] target/mips: Add and integrate MXU decoding engine placeholder X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Aleksandar Markovic Provide the placeholder and add the invocation logic for MXU decoding engine. Reviewed-by: Stefan Markovic Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index 2335721..7c4bc98 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -23978,6 +23978,12 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) } } +static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx) +{ + MIPS_INVAL("decode_opc_mxu"); + generate_exception_end(ctx, EXCP_RI); +} + static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx) { int rs, rt, rd; @@ -26221,6 +26227,8 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) case OPC_SPECIAL2: if ((ctx->insn_flags & INSN_R5900) && (ctx->insn_flags & ASE_MMI)) { decode_tx79_mmi(env, ctx); + } else if (ctx->insn_flags & ASE_MXU) { + decode_opc_mxu(env, ctx); } else { decode_opc_special2_legacy(env, ctx); } From patchwork Mon Oct 29 15:19:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 990320 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42kJhK35sYz9s89 for ; Tue, 30 Oct 2018 02:40:15 +1100 (AEDT) Received: from localhost ([::1]:46317 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9eG-0000EH-Mq for incoming@patchwork.ozlabs.org; Mon, 29 Oct 2018 11:40:12 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34204) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9LR-0008JI-IZ for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:20:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gH9LL-0003I7-QS for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:20:43 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:39356 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gH9LL-0003GP-1p for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:20:39 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 6BF7C1A23C6; Mon, 29 Oct 2018 16:20:25 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 16A7B1A2217; Mon, 29 Oct 2018 16:20:25 +0100 (CET) From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Mon, 29 Oct 2018 16:19:57 +0100 Message-Id: <1540826418-5501-7-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL 06/27] target/mips: Add MXU decoding engine X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Aleksandar Markovic Add MXU decoding engine: add handlers for all instruction pools, and main decode handler. The handlers, for now, for the purpose of this patch, contain only sceleton in the form of a single switch statement. Reviewed-by: Stefan Markovic Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 1143 ++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 1141 insertions(+), 2 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 7c4bc98..d2053d6 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -23978,12 +23978,1151 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) } } +/* + * + * Decode MXU pool00 + * + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+---------+-----+-------+-------+-------+-----------+ + * | SPECIAL2 |0 0 0 0 0|x x x| XRc | XRb | XRa |MXU__POOL00| + * +-----------+---------+-----+-------+-------+-------+-----------+ + * + */ +static void decode_opc_mxu__pool00(CPUMIPSState *env, DisasContext *ctx) +{ + uint32_t opcode = extract32(ctx->opcode, 18, 3); + + switch (opcode) { + case OPC_MXU_S32MAX: + /* TODO: Implement emulation of S32MAX instruction. */ + MIPS_INVAL("OPC_MXU_S32MAX"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_S32MIN: + /* TODO: Implement emulation of S32MIN instruction. */ + MIPS_INVAL("OPC_MXU_S32MIN"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_D16MAX: + /* TODO: Implement emulation of D16MAX instruction. */ + MIPS_INVAL("OPC_MXU_D16MAX"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_D16MIN: + /* TODO: Implement emulation of D16MIN instruction. */ + MIPS_INVAL("OPC_MXU_D16MIN"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_Q8MAX: + /* TODO: Implement emulation of Q8MAX instruction. */ + MIPS_INVAL("OPC_MXU_Q8MAX"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_Q8MIN: + /* TODO: Implement emulation of Q8MIN instruction. */ + MIPS_INVAL("OPC_MXU_Q8MIN"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_Q8SLT: + /* TODO: Implement emulation of Q8SLT instruction. */ + MIPS_INVAL("OPC_MXU_Q8SLT"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_Q8SLTU: + /* TODO: Implement emulation of Q8SLTU instruction. */ + MIPS_INVAL("OPC_MXU_Q8SLTU"); + generate_exception_end(ctx, EXCP_RI); + break; + default: + MIPS_INVAL("decode_opc_mxu"); + generate_exception_end(ctx, EXCP_RI); + break; + } +} + +/* + * + * Decode MXU pool01 + * + * S32SLT, D16SLT, D16AVG, D16AVGR, Q8AVG, Q8AVGR: + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+---------+-----+-------+-------+-------+-----------+ + * | SPECIAL2 |0 0 0 0 0|x x x| XRc | XRb | XRa |MXU__POOL01| + * +-----------+---------+-----+-------+-------+-------+-----------+ + * + * Q8ADD: + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+---+-----+-----+-------+-------+-------+-----------+ + * | SPECIAL2 |en2|0 0 0|x x x| XRc | XRb | XRa |MXU__POOL01| + * +-----------+---+-----+-----+-------+-------+-------+-----------+ + * + */ +static void decode_opc_mxu__pool01(CPUMIPSState *env, DisasContext *ctx) +{ + uint32_t opcode = extract32(ctx->opcode, 18, 3); + + switch (opcode) { + case OPC_MXU_S32SLT: + /* TODO: Implement emulation of S32SLT instruction. */ + MIPS_INVAL("OPC_MXU_S32SLT"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_D16SLT: + /* TODO: Implement emulation of D16SLT instruction. */ + MIPS_INVAL("OPC_MXU_D16SLT"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_D16AVG: + /* TODO: Implement emulation of D16AVG instruction. */ + MIPS_INVAL("OPC_MXU_D16AVG"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_D16AVGR: + /* TODO: Implement emulation of D16AVGR instruction. */ + MIPS_INVAL("OPC_MXU_D16AVGR"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_Q8AVG: + /* TODO: Implement emulation of Q8AVG instruction. */ + MIPS_INVAL("OPC_MXU_Q8AVG"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_Q8AVGR: + /* TODO: Implement emulation of Q8AVGR instruction. */ + MIPS_INVAL("OPC_MXU_Q8AVGR"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_Q8ADD: + /* TODO: Implement emulation of Q8ADD instruction. */ + MIPS_INVAL("OPC_MXU_Q8ADD"); + generate_exception_end(ctx, EXCP_RI); + break; + default: + MIPS_INVAL("decode_opc_mxu"); + generate_exception_end(ctx, EXCP_RI); + break; + } +} + +/* + * + * Decode MXU pool02 + * + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+---------+-----+-------+-------+-------+-----------+ + * | SPECIAL2 |0 0 0 0 0|x x x| XRc | XRb | XRa |MXU__POOL02| + * +-----------+---------+-----+-------+-------+-------+-----------+ + * + */ +static void decode_opc_mxu__pool02(CPUMIPSState *env, DisasContext *ctx) +{ + uint32_t opcode = extract32(ctx->opcode, 18, 3); + + switch (opcode) { + case OPC_MXU_S32CPS: + /* TODO: Implement emulation of S32CPS instruction. */ + MIPS_INVAL("OPC_MXU_S32CPS"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_D16CPS: + /* TODO: Implement emulation of D16CPS instruction. */ + MIPS_INVAL("OPC_MXU_D16CPS"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_Q8ABD: + /* TODO: Implement emulation of Q8ABD instruction. */ + MIPS_INVAL("OPC_MXU_Q8ABD"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_Q16SAT: + /* TODO: Implement emulation of Q16SAT instruction. */ + MIPS_INVAL("OPC_MXU_Q16SAT"); + generate_exception_end(ctx, EXCP_RI); + break; + default: + MIPS_INVAL("decode_opc_mxu"); + generate_exception_end(ctx, EXCP_RI); + break; + } +} + +/* + * + * Decode MXU pool03 + * + * D16MULF: + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+---+---+-------+-------+-------+-------+-----------+ + * | SPECIAL2 |x x|on2|0 0 0 0| XRc | XRb | XRa |MXU__POOL03| + * +-----------+---+---+-------+-------+-------+-------+-----------+ + * + * D16MULE: + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+---+---+-------+-------+-------+-------+-----------+ + * | SPECIAL2 |x x|on2| Xd | XRc | XRb | XRa |MXU__POOL03| + * +-----------+---+---+-------+-------+-------+-------+-----------+ + * + */ +static void decode_opc_mxu__pool03(CPUMIPSState *env, DisasContext *ctx) +{ + uint32_t opcode = extract32(ctx->opcode, 24, 2); + + switch (opcode) { + case OPC_MXU_D16MULF: + /* TODO: Implement emulation of D16MULF instruction. */ + MIPS_INVAL("OPC_MXU_D16MULF"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_D16MULE: + /* TODO: Implement emulation of D16MULE instruction. */ + MIPS_INVAL("OPC_MXU_D16MULE"); + generate_exception_end(ctx, EXCP_RI); + break; + default: + MIPS_INVAL("decode_opc_mxu"); + generate_exception_end(ctx, EXCP_RI); + break; + } +} + +/* + * + * Decode MXU pool04 + * + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+---------+-+-------------------+-------+-----------+ + * | SPECIAL2 | rb |x| s12 | XRa |MXU__POOL04| + * +-----------+---------+-+-------------------+-------+-----------+ + * + */ +static void decode_opc_mxu__pool04(CPUMIPSState *env, DisasContext *ctx) +{ + uint32_t opcode = extract32(ctx->opcode, 20, 1); + + switch (opcode) { + case OPC_MXU_S32LDD: + /* TODO: Implement emulation of S32LDD instruction. */ + MIPS_INVAL("OPC_MXU_S32LDD"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_S32LDDR: + /* TODO: Implement emulation of S32LDDR instruction. */ + MIPS_INVAL("OPC_MXU_S32LDDR"); + generate_exception_end(ctx, EXCP_RI); + break; + default: + MIPS_INVAL("decode_opc_mxu"); + generate_exception_end(ctx, EXCP_RI); + break; + } +} + +/* + * + * Decode MXU pool05 + * + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+---------+-+-------------------+-------+-----------+ + * | SPECIAL2 | rb |x| s12 | XRa |MXU__POOL05| + * +-----------+---------+-+-------------------+-------+-----------+ + * + */ +static void decode_opc_mxu__pool05(CPUMIPSState *env, DisasContext *ctx) +{ + uint32_t opcode = extract32(ctx->opcode, 20, 1); + + switch (opcode) { + case OPC_MXU_S32STD: + /* TODO: Implement emulation of S32STD instruction. */ + MIPS_INVAL("OPC_MXU_S32STD"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_S32STDR: + /* TODO: Implement emulation of S32STDR instruction. */ + MIPS_INVAL("OPC_MXU_S32STDR"); + generate_exception_end(ctx, EXCP_RI); + break; + default: + MIPS_INVAL("decode_opc_mxu"); + generate_exception_end(ctx, EXCP_RI); + break; + } +} + +/* + * + * Decode MXU pool06 + * + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+---------+---------+---+-------+-------+-----------+ + * | SPECIAL2 | rb | rc |st2|x x x x| XRa |MXU__POOL06| + * +-----------+---------+---------+---+-------+-------+-----------+ + * + */ +static void decode_opc_mxu__pool06(CPUMIPSState *env, DisasContext *ctx) +{ + uint32_t opcode = extract32(ctx->opcode, 10, 4); + + switch (opcode) { + case OPC_MXU_S32LDDV: + /* TODO: Implement emulation of S32LDDV instruction. */ + MIPS_INVAL("OPC_MXU_S32LDDV"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_S32LDDVR: + /* TODO: Implement emulation of S32LDDVR instruction. */ + MIPS_INVAL("OPC_MXU_S32LDDVR"); + generate_exception_end(ctx, EXCP_RI); + break; + default: + MIPS_INVAL("decode_opc_mxu"); + generate_exception_end(ctx, EXCP_RI); + break; + } +} + +/* + * + * Decode MXU pool07 + * + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+---------+---------+---+-------+-------+-----------+ + * | SPECIAL2 | rb | rc |st2|x x x x| XRa |MXU__POOL07| + * +-----------+---------+---------+---+-------+-------+-----------+ + * + */ +static void decode_opc_mxu__pool07(CPUMIPSState *env, DisasContext *ctx) +{ + uint32_t opcode = extract32(ctx->opcode, 10, 4); + + switch (opcode) { + case OPC_MXU_S32STDV: + /* TODO: Implement emulation of S32TDV instruction. */ + MIPS_INVAL("OPC_MXU_S32TDV"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_S32STDVR: + /* TODO: Implement emulation of S32TDVR instruction. */ + MIPS_INVAL("OPC_MXU_S32TDVR"); + generate_exception_end(ctx, EXCP_RI); + break; + default: + MIPS_INVAL("decode_opc_mxu"); + generate_exception_end(ctx, EXCP_RI); + break; + } +} + +/* + * + * Decode MXU pool08 + * + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+---------+-+-------------------+-------+-----------+ + * | SPECIAL2 | rb |x| s12 | XRa |MXU__POOL08| + * +-----------+---------+-+-------------------+-------+-----------+ + * +*/ +static void decode_opc_mxu__pool08(CPUMIPSState *env, DisasContext *ctx) +{ + uint32_t opcode = extract32(ctx->opcode, 20, 1); + + switch (opcode) { + case OPC_MXU_S32LDI: + /* TODO: Implement emulation of S32LDI instruction. */ + MIPS_INVAL("OPC_MXU_S32LDI"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_S32LDIR: + /* TODO: Implement emulation of S32LDIR instruction. */ + MIPS_INVAL("OPC_MXU_S32LDIR"); + generate_exception_end(ctx, EXCP_RI); + break; + default: + MIPS_INVAL("decode_opc_mxu"); + generate_exception_end(ctx, EXCP_RI); + break; + } +} + +/* + * + * Decode MXU pool09 + * + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+---------+-+-------------------+-------+-----------+ + * | SPECIAL2 | rb |x| s12 | XRa |MXU__POOL09| + * +-----------+---------+-+-------------------+-------+-----------+ + * + */ +static void decode_opc_mxu__pool09(CPUMIPSState *env, DisasContext *ctx) +{ + uint32_t opcode = extract32(ctx->opcode, 5, 0); + + switch (opcode) { + case OPC_MXU_S32SDI: + /* TODO: Implement emulation of S32SDI instruction. */ + MIPS_INVAL("OPC_MXU_S32SDI"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_S32SDIR: + /* TODO: Implement emulation of S32SDIR instruction. */ + MIPS_INVAL("OPC_MXU_S32SDIR"); + generate_exception_end(ctx, EXCP_RI); + break; + default: + MIPS_INVAL("decode_opc_mxu"); + generate_exception_end(ctx, EXCP_RI); + break; + } +} + +/* + * + * Decode MXU pool10 + * + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+---------+---------+---+-------+-------+-----------+ + * | SPECIAL2 | rb | rc |st2|x x x x| XRa |MXU__POOL10| + * +-----------+---------+---------+---+-------+-------+-----------+ + * + */ +static void decode_opc_mxu__pool10(CPUMIPSState *env, DisasContext *ctx) +{ + uint32_t opcode = extract32(ctx->opcode, 5, 0); + + switch (opcode) { + case OPC_MXU_S32LDIV: + /* TODO: Implement emulation of S32LDIV instruction. */ + MIPS_INVAL("OPC_MXU_S32LDIV"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_S32LDIVR: + /* TODO: Implement emulation of S32LDIVR instruction. */ + MIPS_INVAL("OPC_MXU_S32LDIVR"); + generate_exception_end(ctx, EXCP_RI); + break; + default: + MIPS_INVAL("decode_opc_mxu"); + generate_exception_end(ctx, EXCP_RI); + break; + } +} + +/* + * + * Decode MXU pool11 + * + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+---------+---------+---+-------+-------+-----------+ + * | SPECIAL2 | rb | rc |st2|x x x x| XRa |MXU__POOL11| + * +-----------+---------+---------+---+-------+-------+-----------+ + * + */ +static void decode_opc_mxu__pool11(CPUMIPSState *env, DisasContext *ctx) +{ + uint32_t opcode = extract32(ctx->opcode, 10, 4); + + switch (opcode) { + case OPC_MXU_S32SDIV: + /* TODO: Implement emulation of S32SDIV instruction. */ + MIPS_INVAL("OPC_MXU_S32SDIV"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_S32SDIVR: + /* TODO: Implement emulation of S32SDIVR instruction. */ + MIPS_INVAL("OPC_MXU_S32SDIVR"); + generate_exception_end(ctx, EXCP_RI); + break; + default: + MIPS_INVAL("decode_opc_mxu"); + generate_exception_end(ctx, EXCP_RI); + break; + } +} + +/* + * + * Decode MXU pool12 + * + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+---+---+-------+-------+-------+-------+-----------+ + * | SPECIAL2 |an2|x x| Xd | XRc | XRb | XRa |MXU__POOL12| + * +-----------+---+---+-------+-------+-------+-------+-----------+ + * + */ +static void decode_opc_mxu__pool12(CPUMIPSState *env, DisasContext *ctx) +{ + uint32_t opcode = extract32(ctx->opcode, 22, 2); + + switch (opcode) { + case OPC_MXU_D32ACC: + /* TODO: Implement emulation of D32ACC instruction. */ + MIPS_INVAL("OPC_MXU_D32ACC"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_D32ACCM: + /* TODO: Implement emulation of D32ACCM instruction. */ + MIPS_INVAL("OPC_MXU_D32ACCM"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_D32ASUM: + /* TODO: Implement emulation of D32ASUM instruction. */ + MIPS_INVAL("OPC_MXU_D32ASUM"); + generate_exception_end(ctx, EXCP_RI); + break; + default: + MIPS_INVAL("decode_opc_mxu"); + generate_exception_end(ctx, EXCP_RI); + break; + } +} + +/* + * + * Decode MXU pool13 + * + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+---+---+-------+-------+-------+-------+-----------+ + * | SPECIAL2 |en2|x x|0 0 0 0| XRc | XRb | XRa |MXU__POOL13| + * +-----------+---+---+-------+-------+-------+-------+-----------+ + * + */ +static void decode_opc_mxu__pool13(CPUMIPSState *env, DisasContext *ctx) +{ + uint32_t opcode = extract32(ctx->opcode, 22, 2); + + switch (opcode) { + case OPC_MXU_Q16ACC: + /* TODO: Implement emulation of Q16ACC instruction. */ + MIPS_INVAL("OPC_MXU_Q16ACC"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_Q16ACCM: + /* TODO: Implement emulation of Q16ACCM instruction. */ + MIPS_INVAL("OPC_MXU_Q16ACCM"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_Q16ASUM: + /* TODO: Implement emulation of Q16ASUM instruction. */ + MIPS_INVAL("OPC_MXU_Q16ASUM"); + generate_exception_end(ctx, EXCP_RI); + break; + default: + MIPS_INVAL("decode_opc_mxu"); + generate_exception_end(ctx, EXCP_RI); + break; + } +} + +/* + * + * Decode MXU pool14 + * + * Q8ADDE, Q8ACCE: + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+---+---+-------+-------+-------+-------+-----------+ + * | SPECIAL2 |0 0|x x| XRd | XRc | XRb | XRa |MXU__POOL14| + * +-----------+---+---+-------+-------+-------+-------+-----------+ + * + * D8SUM, D8SUMC: + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+---+---+-------+-------+-------+-------+-----------+ + * | SPECIAL2 |en2|x x|0 0 0 0| XRc | XRb | XRa |MXU__POOL14| + * +-----------+---+---+-------+-------+-------+-------+-----------+ + * + */ +static void decode_opc_mxu__pool14(CPUMIPSState *env, DisasContext *ctx) +{ + uint32_t opcode = extract32(ctx->opcode, 22, 2); + + switch (opcode) { + case OPC_MXU_Q8ADDE: + /* TODO: Implement emulation of Q8ADDE instruction. */ + MIPS_INVAL("OPC_MXU_Q8ADDE"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_D8SUM: + /* TODO: Implement emulation of D8SUM instruction. */ + MIPS_INVAL("OPC_MXU_D8SUM"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_D8SUMC: + /* TODO: Implement emulation of D8SUMC instruction. */ + MIPS_INVAL("OPC_MXU_D8SUMC"); + generate_exception_end(ctx, EXCP_RI); + break; + default: + MIPS_INVAL("decode_opc_mxu"); + generate_exception_end(ctx, EXCP_RI); + break; + } +} + +/* + * + * Decode MXU pool15 + * + * S32MUL, S32MULU, S32EXTRV: + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+---------+---------+---+-------+-------+-----------+ + * | SPECIAL2 | rs | rt |x x| XRd | XRa |MXU__POOL15| + * +-----------+---------+---------+---+-------+-------+-----------+ + * + * S32EXTR: + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+---------+---------+---+-------+-------+-----------+ + * | SPECIAL2 | rb | sft5 |x x| XRd | XRa |MXU__POOL15| + * +-----------+---------+---------+---+-------+-------+-----------+ + * + */ +static void decode_opc_mxu__pool15(CPUMIPSState *env, DisasContext *ctx) +{ + uint32_t opcode = extract32(ctx->opcode, 14, 2); + + switch (opcode) { + case OPC_MXU_S32MUL: + /* TODO: Implement emulation of S32MUL instruction. */ + MIPS_INVAL("OPC_MXU_S32MUL"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_S32MULU: + /* TODO: Implement emulation of S32MULU instruction. */ + MIPS_INVAL("OPC_MXU_S32MULU"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_S32EXTR: + /* TODO: Implement emulation of S32EXTR instruction. */ + MIPS_INVAL("OPC_MXU_S32EXTR"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_S32EXTRV: + /* TODO: Implement emulation of S32EXTRV instruction. */ + MIPS_INVAL("OPC_MXU_S32EXTRV"); + generate_exception_end(ctx, EXCP_RI); + break; + default: + MIPS_INVAL("decode_opc_mxu"); + generate_exception_end(ctx, EXCP_RI); + break; + } +} + +/* + * + * Decode MXU pool16 + * + * D32SARW: + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+---------+-----+-------+-------+-------+-----------+ + * | SPECIAL2 | rb |x x x| XRc | XRb | XRa |MXU__POOL16| + * +-----------+---------+-----+-------+-------+-------+-----------+ + * + * S32ALN: + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+---------+-----+-------+-------+-------+-----------+ + * | SPECIAL2 | rs |x x x| XRc | XRb | XRa |MXU__POOL16| + * +-----------+---------+-----+-------+-------+-------+-----------+ + * + * S32ALNI: + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+-----+---+-----+-------+-------+-------+-----------+ + * | SPECIAL2 | s3 |0 0|x x x| XRc | XRb | XRa |MXU__POOL16| + * +-----------+-----+---+-----+-------+-------+-------+-----------+ + * + * S32NOR, S32AND, S32OR, S32XOR: + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+---------+-----+-------+-------+-------+-----------+ + * | SPECIAL2 |0 0 0 0 0|x x x| XRc | XRb | XRa |MXU__POOL16| + * +-----------+---------+-----+-------+-------+-------+-----------+ + * + * S32LUI: + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+-----+---+-----+-------+---------------+-----------+ + * | SPECIAL2 |optn3|0 0|x x x| XRc | s8 |MXU__POOL16| + * +-----------+-----+---+-----+-------+---------------+-----------+ + * + */ +static void decode_opc_mxu__pool16(CPUMIPSState *env, DisasContext *ctx) +{ + uint32_t opcode = extract32(ctx->opcode, 18, 3); + + switch (opcode) { + case OPC_MXU_D32SARW: + /* TODO: Implement emulation of D32SARW instruction. */ + MIPS_INVAL("OPC_MXU_D32SARW"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_S32ALN: + /* TODO: Implement emulation of S32ALN instruction. */ + MIPS_INVAL("OPC_MXU_S32ALN"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_S32ALNI: + /* TODO: Implement emulation of S32ALNI instruction. */ + MIPS_INVAL("OPC_MXU_S32ALNI"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_S32NOR: + /* TODO: Implement emulation of S32NOR instruction. */ + MIPS_INVAL("OPC_MXU_S32NOR"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_S32AND: + /* TODO: Implement emulation of S32AND instruction. */ + MIPS_INVAL("OPC_MXU_S32AND"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_S32OR: + /* TODO: Implement emulation of S32OR instruction. */ + MIPS_INVAL("OPC_MXU_S32OR"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_S32XOR: + /* TODO: Implement emulation of S32XOR instruction. */ + MIPS_INVAL("OPC_MXU_S32XOR"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_S32LUI: + /* TODO: Implement emulation of S32LUI instruction. */ + MIPS_INVAL("OPC_MXU_S32LUI"); + generate_exception_end(ctx, EXCP_RI); + break; + default: + MIPS_INVAL("decode_opc_mxu"); + generate_exception_end(ctx, EXCP_RI); + break; + } +} + +/* + * + * Decode MXU pool17 + * + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+---------+-----+-------+-------+-------+-----------+ + * | SPECIAL2 | rb |x x x| XRd | XRa |0 0 0 0|MXU__POOL17| + * +-----------+---------+-----+-------+-------+-------+-----------+ + * + */ +static void decode_opc_mxu__pool17(CPUMIPSState *env, DisasContext *ctx) +{ + uint32_t opcode = extract32(ctx->opcode, 18, 3); + + switch (opcode) { + case OPC_MXU_D32SLLV: + /* TODO: Implement emulation of D32SLLV instruction. */ + MIPS_INVAL("OPC_MXU_D32SLLV"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_D32SLRV: + /* TODO: Implement emulation of D32SLRV instruction. */ + MIPS_INVAL("OPC_MXU_D32SLRV"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_D32SARV: + /* TODO: Implement emulation of D32SARV instruction. */ + MIPS_INVAL("OPC_MXU_D32SARV"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_Q16SLLV: + /* TODO: Implement emulation of Q16SLLV instruction. */ + MIPS_INVAL("OPC_MXU_Q16SLLV"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_Q16SLRV: + /* TODO: Implement emulation of Q16SLRV instruction. */ + MIPS_INVAL("OPC_MXU_Q16SLRV"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_Q16SARV: + /* TODO: Implement emulation of Q16SARV instruction. */ + MIPS_INVAL("OPC_MXU_Q16SARV"); + generate_exception_end(ctx, EXCP_RI); + break; + default: + MIPS_INVAL("decode_opc_mxu"); + generate_exception_end(ctx, EXCP_RI); + break; + } +} + +/* + * + * Decode MXU pool18 + * + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+---+---+-------+-------+-------+-------+-----------+ + * | SPECIAL2 |0 0|x x| XRd | XRc | XRb | XRa |MXU__POOL18| + * +-----------+---+---+-------+-------+-------+-------+-----------+ + * + */ +static void decode_opc_mxu__pool18(CPUMIPSState *env, DisasContext *ctx) +{ + uint32_t opcode = extract32(ctx->opcode, 22, 2); + + switch (opcode) { + case OPC_MXU_Q8MUL: + /* TODO: Implement emulation of Q8MUL instruction. */ + MIPS_INVAL("OPC_MXU_Q8MUL"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_Q8MULSU: + /* TODO: Implement emulation of Q8MULSU instruction. */ + MIPS_INVAL("OPC_MXU_Q8MULSU"); + generate_exception_end(ctx, EXCP_RI); + break; + default: + MIPS_INVAL("decode_opc_mxu"); + generate_exception_end(ctx, EXCP_RI); + break; + } +} + +/* + * + * Decode MXU pool19 + * + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+---------+-----+-------+-------+-------+-----------+ + * | SPECIAL2 |0 0 0 0 0|x x x| XRc | XRb | XRa |MXU__POOL19| + * +-----------+---------+-----+-------+-------+-------+-----------+ + * + */ +static void decode_opc_mxu__pool19(CPUMIPSState *env, DisasContext *ctx) +{ + uint32_t opcode = extract32(ctx->opcode, 18, 3); + + switch (opcode) { + case OPC_MXU_Q8MOVZ: + /* TODO: Implement emulation of Q8MOVZ instruction. */ + MIPS_INVAL("OPC_MXU_Q8MOVZ"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_Q8MOVN: + /* TODO: Implement emulation of Q8MOVN instruction. */ + MIPS_INVAL("OPC_MXU_Q8MOVN"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_D16MOVZ: + /* TODO: Implement emulation of D16MOVZ instruction. */ + MIPS_INVAL("OPC_MXU_D16MOVZ"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_D16MOVN: + /* TODO: Implement emulation of D16MOVN instruction. */ + MIPS_INVAL("OPC_MXU_D16MOVN"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_S32MOVZ: + /* TODO: Implement emulation of S32MOVZ instruction. */ + MIPS_INVAL("OPC_MXU_S32MOVZ"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_S32MOVN: + /* TODO: Implement emulation of S32MOVN instruction. */ + MIPS_INVAL("OPC_MXU_S32MOVN"); + generate_exception_end(ctx, EXCP_RI); + break; + default: + MIPS_INVAL("decode_opc_mxu"); + generate_exception_end(ctx, EXCP_RI); + break; + } +} + +/* + * + * Decode MXU pool20 + * + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+---+---+-------+-------+-------+-------+-----------+ + * | SPECIAL2 |an2|x x| XRd | XRc | XRb | XRa |MXU__POOL20| + * +-----------+---+---+-------+-------+-------+-------+-----------+ + * + */ +static void decode_opc_mxu__pool20(CPUMIPSState *env, DisasContext *ctx) +{ + uint32_t opcode = extract32(ctx->opcode, 22, 2); + + switch (opcode) { + case OPC_MXU_Q8MAC: + /* TODO: Implement emulation of Q8MAC instruction. */ + MIPS_INVAL("OPC_MXU_Q8MAC"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_Q8MACSU: + /* TODO: Implement emulation of Q8MACSU instruction. */ + MIPS_INVAL("OPC_MXU_Q8MACSU"); + generate_exception_end(ctx, EXCP_RI); + break; + default: + MIPS_INVAL("decode_opc_mxu"); + generate_exception_end(ctx, EXCP_RI); + break; + } +} + + +/* + * Main MXU decoding function + * + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+---------------------------------------+-----------+ + * | SPECIAL2 | |x x x x x x| + * +-----------+---------------------------------------+-----------+ + * + */ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx) { - MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + uint32_t opcode = extract32(ctx->opcode, 0, 6); + + switch (opcode) { + case OPC_MXU_S32MADD: + /* TODO: Implement emulation of S32MADD instruction. */ + MIPS_INVAL("OPC_MXU_S32MADD"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_S32MADDU: + /* TODO: Implement emulation of S32MADDU instruction. */ + MIPS_INVAL("OPC_MXU_S32MADDU"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU__POOL00: + decode_opc_mxu__pool00(env, ctx); + break; + case OPC_MXU_S32MSUB: + /* TODO: Implement emulation of S32MSUB instruction. */ + MIPS_INVAL("OPC_MXU_S32MSUB"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_S32MSUBU: + /* TODO: Implement emulation of S32MSUBU instruction. */ + MIPS_INVAL("OPC_MXU_S32MSUBU"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU__POOL01: + decode_opc_mxu__pool01(env, ctx); + break; + case OPC_MXU__POOL02: + decode_opc_mxu__pool02(env, ctx); + break; + case OPC_MXU_D16MUL: + /* TODO: Implement emulation of D16MUL instruction. */ + MIPS_INVAL("OPC_MXU_D16MUL"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU__POOL03: + decode_opc_mxu__pool03(env, ctx); + break; + case OPC_MXU_D16MAC: + /* TODO: Implement emulation of D16MAC instruction. */ + MIPS_INVAL("OPC_MXU_D16MAC"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_D16MACF: + /* TODO: Implement emulation of D16MACF instruction. */ + MIPS_INVAL("OPC_MXU_D16MACF"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_D16MADL: + /* TODO: Implement emulation of D16MADL instruction. */ + MIPS_INVAL("OPC_MXU_D16MADL"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_S16MAD: + /* TODO: Implement emulation of S16MAD instruction. */ + MIPS_INVAL("OPC_MXU_S16MAD"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_Q16ADD: + /* TODO: Implement emulation of Q16ADD instruction. */ + MIPS_INVAL("OPC_MXU_Q16ADD"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_D16MACE: + /* TODO: Implement emulation of D16MACE instruction. */ + MIPS_INVAL("OPC_MXU_D16MACE"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU__POOL04: + decode_opc_mxu__pool04(env, ctx); + break; + case OPC_MXU__POOL05: + decode_opc_mxu__pool05(env, ctx); + break; + case OPC_MXU__POOL06: + decode_opc_mxu__pool06(env, ctx); + break; + case OPC_MXU__POOL07: + decode_opc_mxu__pool07(env, ctx); + break; + case OPC_MXU__POOL08: + decode_opc_mxu__pool08(env, ctx); + break; + case OPC_MXU__POOL09: + decode_opc_mxu__pool09(env, ctx); + break; + case OPC_MXU__POOL10: + decode_opc_mxu__pool10(env, ctx); + break; + case OPC_MXU__POOL11: + decode_opc_mxu__pool11(env, ctx); + break; + case OPC_MXU_D32ADD: + /* TODO: Implement emulation of D32ADD instruction. */ + MIPS_INVAL("OPC_MXU_D32ADD"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU__POOL12: + decode_opc_mxu__pool12(env, ctx); + break; + case OPC_MXU__POOL13: + decode_opc_mxu__pool13(env, ctx); + break; + case OPC_MXU__POOL14: + decode_opc_mxu__pool14(env, ctx); + break; + case OPC_MXU_Q8ACCE: + /* TODO: Implement emulation of Q8ACCE instruction. */ + MIPS_INVAL("OPC_MXU_Q8ACCE"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_S8LDD: + /* TODO: Implement emulation of S8LDD instruction. */ + MIPS_INVAL("OPC_MXU_S8LDD"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_S8STD: + /* TODO: Implement emulation of S8STD instruction. */ + MIPS_INVAL("OPC_MXU_S8STD"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_S8LDI: + /* TODO: Implement emulation of S8LDI instruction. */ + MIPS_INVAL("OPC_MXU_S8LDI"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_S8SDI: + /* TODO: Implement emulation of S8SDI instruction. */ + MIPS_INVAL("OPC_MXU_S8SDI"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU__POOL15: + decode_opc_mxu__pool15(env, ctx); + break; + case OPC_MXU__POOL16: + decode_opc_mxu__pool16(env, ctx); + break; + case OPC_MXU_LXB: + /* TODO: Implement emulation of LXB instruction. */ + MIPS_INVAL("OPC_MXU_LXB"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_S16LDD: + /* TODO: Implement emulation of S16LDD instruction. */ + MIPS_INVAL("OPC_MXU_S16LDD"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_S16STD: + /* TODO: Implement emulation of S16STD instruction. */ + MIPS_INVAL("OPC_MXU_S16STD"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_S16LDI: + /* TODO: Implement emulation of S16LDI instruction. */ + MIPS_INVAL("OPC_MXU_S16LDI"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_S16SDI: + /* TODO: Implement emulation of S16SDI instruction. */ + MIPS_INVAL("OPC_MXU_S16SDI"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_S32M2I: + /* TODO: Implement emulation of S32M2I instruction. */ + MIPS_INVAL("OPC_MXU_S32M2I"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_S32I2M: + /* TODO: Implement emulation of S32I2M instruction. */ + MIPS_INVAL("OPC_MXU_S32I2M"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_D32SLL: + /* TODO: Implement emulation of D32SLL instruction. */ + MIPS_INVAL("OPC_MXU_D32SLL"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_D32SLR: + /* TODO: Implement emulation of D32SLR instruction. */ + MIPS_INVAL("OPC_MXU_D32SLR"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_D32SARL: + /* TODO: Implement emulation of D32SARL instruction. */ + MIPS_INVAL("OPC_MXU_D32SARL"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_D32SAR: + /* TODO: Implement emulation of D32SAR instruction. */ + MIPS_INVAL("OPC_MXU_D32SAR"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_Q16SLL: + /* TODO: Implement emulation of Q16SLL instruction. */ + MIPS_INVAL("OPC_MXU_Q16SLL"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_Q16SLR: + /* TODO: Implement emulation of Q16SLR instruction. */ + MIPS_INVAL("OPC_MXU_Q16SLR"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU__POOL17: + decode_opc_mxu__pool17(env, ctx); + break; + case OPC_MXU_Q16SAR: + /* TODO: Implement emulation of Q16SAR instruction. */ + MIPS_INVAL("OPC_MXU_Q16SAR"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU__POOL18: + decode_opc_mxu__pool18(env, ctx); + break; + case OPC_MXU__POOL19: + decode_opc_mxu__pool19(env, ctx); + break; + case OPC_MXU__POOL20: + decode_opc_mxu__pool20(env, ctx); + break; + case OPC_MXU_Q16SCOP: + /* TODO: Implement emulation of Q16SCOP instruction. */ + MIPS_INVAL("OPC_MXU_Q16SCOP"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_Q8MADL: + /* TODO: Implement emulation of Q8MADL instruction. */ + MIPS_INVAL("OPC_MXU_Q8MADL"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_S32SFL: + /* TODO: Implement emulation of S32SFL instruction. */ + MIPS_INVAL("OPC_MXU_S32SFL"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_Q8SAD: + /* TODO: Implement emulation of Q8SAD instruction. */ + MIPS_INVAL("OPC_MXU_Q8SAD"); + generate_exception_end(ctx, EXCP_RI); + break; + default: + MIPS_INVAL("decode_opc_mxu"); + generate_exception_end(ctx, EXCP_RI); + } } + static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx) { int rs, rt, rd; From patchwork Mon Oct 29 15:19:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 990305 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42kJPK2NRKz9s55 for ; Tue, 30 Oct 2018 02:27:17 +1100 (AEDT) Received: from localhost ([::1]:46250 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9Ri-0005Kl-Ps for incoming@patchwork.ozlabs.org; Mon, 29 Oct 2018 11:27:14 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34197) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9LR-0008JD-IQ for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:20:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gH9LL-0003Hp-K8 for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:20:43 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:39352 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gH9LK-0003GM-V1 for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:20:39 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 536AA1A23A3; Mon, 29 Oct 2018 16:20:25 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 2D8041A22CF; Mon, 29 Oct 2018 16:20:25 +0100 (CET) From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Mon, 29 Oct 2018 16:19:58 +0100 Message-Id: <1540826418-5501-8-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL 07/27] target/mips: Add bit encoding for MXU accumulate add/sub 1-bit pattern 'aptn1' X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Aleksandar Markovic Add bit encoding for MXU accumulate add/subtract 1-bit pattern 'aptn1'. Reviewed-by: Stefan Markovic Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index d2053d6..848b0ef 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -23978,6 +23978,12 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) } } + +/* MXU accumulate add/subtract 1-bit pattern 'aptn1' */ +#define MXU_APTN1_A 0 +#define MXU_APTN1_S 1 + + /* * * Decode MXU pool00 From patchwork Mon Oct 29 15:19:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 990304 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42kJPG0GZ7z9s55 for ; Tue, 30 Oct 2018 02:27:14 +1100 (AEDT) Received: from localhost ([::1]:46249 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9Rf-0005IR-Id for incoming@patchwork.ozlabs.org; Mon, 29 Oct 2018 11:27:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34196) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9LR-0008JC-IK for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:20:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gH9LN-0003Il-Nb for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:20:43 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:39351 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gH9LL-0003GN-Io for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:20:39 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 6200F1A23D9; Mon, 29 Oct 2018 16:20:25 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 34DAE1A23B7; Mon, 29 Oct 2018 16:20:25 +0100 (CET) From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Mon, 29 Oct 2018 16:19:59 +0100 Message-Id: <1540826418-5501-9-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL 08/27] target/mips: Add bit encoding for MXU accumulate add/sub 2-bit pattern 'aptn2' X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Craig Janeczek Add bit encoding for MXU accumulate add/subtract 2-bit pattern 'aptn2'. Reviewed-by: Stefan Markovic Signed-off-by: Craig Janeczek Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index 848b0ef..4ccb1a9 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -23983,6 +23983,12 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) #define MXU_APTN1_A 0 #define MXU_APTN1_S 1 +/* MXU accumulate add/subtract 2-bit pattern 'aptn2' */ +#define MXU_APTN2_AA 0 +#define MXU_APTN2_AS 1 +#define MXU_APTN2_SA 2 +#define MXU_APTN2_SS 3 + /* * From patchwork Mon Oct 29 15:20:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 990312 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42kJXL6v2Rz9s3Z for ; Tue, 30 Oct 2018 02:33:22 +1100 (AEDT) Received: from localhost ([::1]:46279 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9Xc-0003AB-0N for incoming@patchwork.ozlabs.org; Mon, 29 Oct 2018 11:33:20 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34206) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9LR-0008JK-Id for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:20:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gH9LN-0003Ir-Oj for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:20:43 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:39386 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gH9LL-0003GW-Jg for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:20:39 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 6F1FB1A22CF; Mon, 29 Oct 2018 16:20:25 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 3CC491A23D0; Mon, 29 Oct 2018 16:20:25 +0100 (CET) From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Mon, 29 Oct 2018 16:20:00 +0100 Message-Id: <1540826418-5501-10-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL 09/27] target/mips: Add bit encoding for MXU execute add/sub pattern 'eptn2' X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Aleksandar Markovic Add bit encoding for MXU execute 2-bit add/subtract pattern 'eptn2'. Reviewed-by: Stefan Markovic Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index 4ccb1a9..e790fb4 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -23989,6 +23989,12 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) #define MXU_APTN2_SA 2 #define MXU_APTN2_SS 3 +/* MXU execute add/subtract 2-bit pattern 'eptn2' */ +#define MXU_EPTN2_AA 0 +#define MXU_EPTN2_AS 1 +#define MXU_EPTN2_SA 2 +#define MXU_EPTN2_SS 3 + /* * From patchwork Mon Oct 29 15:20:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 990309 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42kJSd2PX3z9s55 for ; Tue, 30 Oct 2018 02:30:09 +1100 (AEDT) Received: from localhost ([::1]:46263 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9UU-0000nv-MF for incoming@patchwork.ozlabs.org; Mon, 29 Oct 2018 11:30:06 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34203) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9LR-0008JH-Ib for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:20:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gH9LL-0003Hz-NB for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:20:43 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:39387 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gH9LL-0003GX-Bi for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:20:39 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 79D361A23E1; Mon, 29 Oct 2018 16:20:25 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 477181A2254; Mon, 29 Oct 2018 16:20:25 +0100 (CET) From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Mon, 29 Oct 2018 16:20:01 +0100 Message-Id: <1540826418-5501-11-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL 10/27] target/mips: Add bit encoding for MXU operand getting pattern 'optn2' X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Craig Janeczek Add bit encoding for MXU operand getting pattern 'optn2'. Reviewed-by: Stefan Markovic Signed-off-by: Craig Janeczek Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index e790fb4..16bb9e0 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -23995,6 +23995,12 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) #define MXU_EPTN2_SA 2 #define MXU_EPTN2_SS 3 +/* MXU operand getting pattern 'optn2' */ +#define MXU_OPTN2_WW 0 +#define MXU_OPTN2_LW 1 +#define MXU_OPTN2_HW 2 +#define MXU_OPTN2_XW 3 + /* * From patchwork Mon Oct 29 15:20:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 990322 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42kJkt0p7Fz9s3Z for ; Tue, 30 Oct 2018 02:42:30 +1100 (AEDT) Received: from localhost ([::1]:46331 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9gR-0002Gf-Kd for incoming@patchwork.ozlabs.org; Mon, 29 Oct 2018 11:42:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34417) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9Lg-0008Sx-GA for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:21:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gH9Lb-0003Oc-95 for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:21:00 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:39390 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gH9LX-0003Gs-B5 for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:20:51 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 822831A23B7; Mon, 29 Oct 2018 16:20:25 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 4FB3D1A224B; Mon, 29 Oct 2018 16:20:25 +0100 (CET) From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Mon, 29 Oct 2018 16:20:02 +0100 Message-Id: <1540826418-5501-12-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL 11/27] target/mips: Add bit encoding for MXU operand getting pattern 'optn3' X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Craig Janeczek Add bit encoding for MXU operand getting pattern 'optn3'. Reviewed-by: Stefan Markovic Signed-off-by: Craig Janeczek Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index 16bb9e0..ccabd13 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -24001,6 +24001,16 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) #define MXU_OPTN2_HW 2 #define MXU_OPTN2_XW 3 +/* MXU operand getting pattern 'optn3' */ +#define MXU_OPTN3_PTN0 0 +#define MXU_OPTN3_PTN1 1 +#define MXU_OPTN3_PTN2 2 +#define MXU_OPTN3_PTN3 3 +#define MXU_OPTN3_PTN4 4 +#define MXU_OPTN3_PTN5 5 +#define MXU_OPTN3_PTN6 6 +#define MXU_OPTN3_PTN7 7 + /* * From patchwork Mon Oct 29 15:20:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 990302 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42kJKn4yVFz9s55 for ; Tue, 30 Oct 2018 02:24:13 +1100 (AEDT) Received: from localhost ([::1]:46233 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9Ok-0002Bs-KL for incoming@patchwork.ozlabs.org; Mon, 29 Oct 2018 11:24:10 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34205) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9LR-0008JJ-Ib for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:20:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gH9LN-0003J6-S7 for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:20:43 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:39392 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gH9LL-0003Gx-NN for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:20:41 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 88F3A1A2217; Mon, 29 Oct 2018 16:20:25 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 57F441A23C3; Mon, 29 Oct 2018 16:20:25 +0100 (CET) From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Mon, 29 Oct 2018 16:20:03 +0100 Message-Id: <1540826418-5501-13-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL 12/27] target/mips: Add emulation of non-MXU MULL within MXU decoding engine X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Craig Janeczek Add emulation of non-MXU MULL within MXU decoding engine. Reviewed-by: Aleksandar Markovic Signed-off-by: Craig Janeczek Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index ccabd13..bdd46ed 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1648,7 +1648,7 @@ enum { enum { OPC_MXU_S32MADD = 0x00, OPC_MXU_S32MADDU = 0x01, - /* not assigned 0x02 */ + OPC__MXU_MUL = 0x02, OPC_MXU__POOL00 = 0x03, OPC_MXU_S32MSUB = 0x04, OPC_MXU_S32MSUBU = 0x05, @@ -24909,6 +24909,11 @@ static void decode_opc_mxu__pool20(CPUMIPSState *env, DisasContext *ctx) */ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx) { + /* + * TODO: Investigate necessity of including handling of + * CLZ, CLO, SDBB in this function, as they belong to + * SPECIAL2 opcode space for regular pre-R6 MIPS ISAs. + */ uint32_t opcode = extract32(ctx->opcode, 0, 6); switch (opcode) { @@ -24922,6 +24927,18 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx) MIPS_INVAL("OPC_MXU_S32MADDU"); generate_exception_end(ctx, EXCP_RI); break; + case OPC__MXU_MUL: /* 0x2 - unused in MXU specs */ + { + uint32_t rs, rt, rd, op1; + + rs = extract32(ctx->opcode, 21, 5); + rt = extract32(ctx->opcode, 16, 5); + rd = extract32(ctx->opcode, 11, 5); + op1 = MASK_SPECIAL2(ctx->opcode); + + gen_arith(ctx, op1, rd, rs, rt); + } + break; case OPC_MXU__POOL00: decode_opc_mxu__pool00(env, ctx); break; From patchwork Mon Oct 29 15:20:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 990329 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42kJq13Pfrz9s3Z for ; Tue, 30 Oct 2018 02:46:05 +1100 (AEDT) Received: from localhost ([::1]:46352 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9jv-0000Xg-3X for incoming@patchwork.ozlabs.org; Mon, 29 Oct 2018 11:46:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34405) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9Lg-0008St-F0 for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:21:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gH9Lb-0003Op-B2 for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:21:00 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:39417 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gH9LX-0003H7-Iy for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:20:53 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 93F201A23D6; Mon, 29 Oct 2018 16:20:25 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 609691A23CF; Mon, 29 Oct 2018 16:20:25 +0100 (CET) From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Mon, 29 Oct 2018 16:20:04 +0100 Message-Id: <1540826418-5501-14-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL 13/27] target/mips: Add emulation of MXU instructions S32I2M and S32M2I X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Craig Janeczek Add support for emulating the S32I2M and S32M2I MXU instructions. This commit also contains utility functions for reading/writing to MXU registers. This is required for overall MXU instruction support. Reviewed-by: Aleksandar Markovic Signed-off-by: Craig Janeczek Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 91 +++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 85 insertions(+), 6 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index bdd46ed..3b1dd59 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -2569,6 +2569,36 @@ static inline void gen_store_srsgpr (int from, int to) } } +/* MXU General purpose registers moves. */ +static inline void gen_load_mxu_gpr(TCGv t, unsigned int reg) +{ + if (reg == 0) { + tcg_gen_movi_tl(t, 0); + } else if (reg <= 15) { + tcg_gen_mov_tl(t, mxu_gpr[reg - 1]); + } +} + +static inline void gen_store_mxu_gpr(TCGv t, unsigned int reg) +{ + if (reg > 0 && reg <= 15) { + tcg_gen_mov_tl(mxu_gpr[reg - 1], t); + } +} + +/* MXU control register moves. */ +static inline void gen_load_mxu_cr(TCGv t) +{ + tcg_gen_mov_tl(t, mxu_CR); +} + +static inline void gen_store_mxu_cr(TCGv t) +{ + /* TODO: Add handling of RW rules for MXU_CR. */ + tcg_gen_mov_tl(mxu_CR, t); +} + + /* Tests */ static inline void gen_save_pc(target_ulong pc) { @@ -24013,6 +24043,59 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) /* + * S32I2M XRa, rb - Register move from GRF to XRF + */ +static void gen_mxu_s32i2m(DisasContext *ctx) +{ + TCGv t0; + uint32_t XRa, Rb; + + t0 = tcg_temp_new(); + + XRa = extract32(ctx->opcode, 6, 5); + Rb = extract32(ctx->opcode, 16, 5); + + gen_load_gpr(t0, Rb); + if (XRa <= 15) { + gen_store_mxu_gpr(t0, XRa); + } else if (XRa == 16) { + gen_store_mxu_cr(t0); + } + + tcg_temp_free(t0); +} + +/* + * S32M2I XRa, rb - Register move from XRF to GRF + */ +static void gen_mxu_s32m2i(DisasContext *ctx) +{ + TCGv t0; + uint32_t XRa, Rb; + + t0 = tcg_temp_new(); + + XRa = extract32(ctx->opcode, 6, 5); + Rb = extract32(ctx->opcode, 16, 5); + + if (XRa <= 15) { + gen_load_mxu_gpr(t0, XRa); + } else if (XRa == 16) { + gen_load_mxu_cr(t0); + } + + gen_store_gpr(t0, Rb); + + tcg_temp_free(t0); +} + + +/* + * Decoding engine for MXU + * ======================= + */ + +/* * * Decode MXU pool00 * @@ -25091,14 +25174,10 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx) generate_exception_end(ctx, EXCP_RI); break; case OPC_MXU_S32M2I: - /* TODO: Implement emulation of S32M2I instruction. */ - MIPS_INVAL("OPC_MXU_S32M2I"); - generate_exception_end(ctx, EXCP_RI); + gen_mxu_s32m2i(ctx); break; case OPC_MXU_S32I2M: - /* TODO: Implement emulation of S32I2M instruction. */ - MIPS_INVAL("OPC_MXU_S32I2M"); - generate_exception_end(ctx, EXCP_RI); + gen_mxu_s32i2m(ctx); break; case OPC_MXU_D32SLL: /* TODO: Implement emulation of D32SLL instruction. */ From patchwork Mon Oct 29 15:20:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 990319 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42kJgW6Xkfz9s55 for ; Tue, 30 Oct 2018 02:39:35 +1100 (AEDT) Received: from localhost ([::1]:46309 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9dd-00088A-23 for incoming@patchwork.ozlabs.org; Mon, 29 Oct 2018 11:39:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34408) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9Lg-0008Su-F3 for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:21:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gH9Lb-0003P0-Ey for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:21:00 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:39418 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gH9LZ-0003H6-K4 for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:20:55 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 9AF3B1A224B; Mon, 29 Oct 2018 16:20:25 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 6C0A21A23DB; Mon, 29 Oct 2018 16:20:25 +0100 (CET) From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Mon, 29 Oct 2018 16:20:05 +0100 Message-Id: <1540826418-5501-15-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL 14/27] target/mips: Move MUL, S32M2I, S32I2M handling out of main MXU switch X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Aleksandar Markovic Move MUL, S32M2I, S32I2M handling out of switch. These are all instructions that do not depend on MXU_EN flag of MXU_CR. Reviewed-by: Stefan Markovic Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 41 +++++++++++++++++++++++------------------ 1 file changed, 23 insertions(+), 18 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 3b1dd59..9d5bf7a 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -24999,6 +24999,29 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx) */ uint32_t opcode = extract32(ctx->opcode, 0, 6); + if (opcode == OPC__MXU_MUL) { + uint32_t rs, rt, rd, op1; + + rs = extract32(ctx->opcode, 21, 5); + rt = extract32(ctx->opcode, 16, 5); + rd = extract32(ctx->opcode, 11, 5); + op1 = MASK_SPECIAL2(ctx->opcode); + + gen_arith(ctx, op1, rd, rs, rt); + + return; + } + + if (opcode == OPC_MXU_S32M2I) { + gen_mxu_s32m2i(ctx); + return; + } + + if (opcode == OPC_MXU_S32I2M) { + gen_mxu_s32i2m(ctx); + return; + } + switch (opcode) { case OPC_MXU_S32MADD: /* TODO: Implement emulation of S32MADD instruction. */ @@ -25010,18 +25033,6 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx) MIPS_INVAL("OPC_MXU_S32MADDU"); generate_exception_end(ctx, EXCP_RI); break; - case OPC__MXU_MUL: /* 0x2 - unused in MXU specs */ - { - uint32_t rs, rt, rd, op1; - - rs = extract32(ctx->opcode, 21, 5); - rt = extract32(ctx->opcode, 16, 5); - rd = extract32(ctx->opcode, 11, 5); - op1 = MASK_SPECIAL2(ctx->opcode); - - gen_arith(ctx, op1, rd, rs, rt); - } - break; case OPC_MXU__POOL00: decode_opc_mxu__pool00(env, ctx); break; @@ -25173,12 +25184,6 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx) MIPS_INVAL("OPC_MXU_S16SDI"); generate_exception_end(ctx, EXCP_RI); break; - case OPC_MXU_S32M2I: - gen_mxu_s32m2i(ctx); - break; - case OPC_MXU_S32I2M: - gen_mxu_s32i2m(ctx); - break; case OPC_MXU_D32SLL: /* TODO: Implement emulation of D32SLL instruction. */ MIPS_INVAL("OPC_MXU_D32SLL"); From patchwork Mon Oct 29 15:20:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 990342 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42kJtw01kZz9s3Z for ; Tue, 30 Oct 2018 02:49:27 +1100 (AEDT) Received: from localhost ([::1]:46369 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9nA-0003sv-R9 for incoming@patchwork.ozlabs.org; Mon, 29 Oct 2018 11:49:24 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34494) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9Li-0008TZ-BP for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:21:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gH9Lc-0003Po-Ah for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:21:02 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:39509 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gH9Lb-0003ID-La for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:20:55 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id B13241A23DA; Mon, 29 Oct 2018 16:20:25 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 75C5D1A2289; Mon, 29 Oct 2018 16:20:25 +0100 (CET) From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Mon, 29 Oct 2018 16:20:06 +0100 Message-Id: <1540826418-5501-16-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL 15/27] target/mips: Add emulation of MXU instruction S8LDD X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Craig Janeczek Add support for emulating the S8LDD MXU instruction. Reviewed-by: Aleksandar Markovic Signed-off-by: Craig Janeczek Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 90 +++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 87 insertions(+), 3 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 9d5bf7a..cb7a24b 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -24089,6 +24089,92 @@ static void gen_mxu_s32m2i(DisasContext *ctx) tcg_temp_free(t0); } +/* + * S8LDD XRa, Rb, s8, optn3 - Load a byte from memory to XRF + */ +static void gen_mxu_s8ldd(DisasContext *ctx) +{ + TCGv t0, t1; + TCGLabel *l0; + uint32_t XRa, Rb, s8, optn3; + + t0 = tcg_temp_new(); + t1 = tcg_temp_new(); + + l0 = gen_new_label(); + + XRa = extract32(ctx->opcode, 6, 4); + s8 = extract32(ctx->opcode, 10, 8); + optn3 = extract32(ctx->opcode, 18, 3); + Rb = extract32(ctx->opcode, 21, 5); + + gen_load_mxu_cr(t0); + tcg_gen_andi_tl(t0, t0, MXU_CR_MXU_EN); + tcg_gen_brcondi_tl(TCG_COND_NE, t0, MXU_CR_MXU_EN, l0); + + gen_load_gpr(t0, Rb); + tcg_gen_addi_tl(t0, t0, (int8_t)s8); + + switch (optn3) { + /* XRa[7:0] = tmp8 */ + case MXU_OPTN3_PTN0: + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); + gen_load_mxu_gpr(t0, XRa); + tcg_gen_deposit_tl(t0, t0, t1, 0, 8); + break; + /* XRa[15:8] = tmp8 */ + case MXU_OPTN3_PTN1: + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); + gen_load_mxu_gpr(t0, XRa); + tcg_gen_deposit_tl(t0, t0, t1, 8, 8); + break; + /* XRa[23:16] = tmp8 */ + case MXU_OPTN3_PTN2: + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); + gen_load_mxu_gpr(t0, XRa); + tcg_gen_deposit_tl(t0, t0, t1, 16, 8); + break; + /* XRa[31:24] = tmp8 */ + case MXU_OPTN3_PTN3: + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); + gen_load_mxu_gpr(t0, XRa); + tcg_gen_deposit_tl(t0, t0, t1, 24, 8); + break; + /* XRa = {8'b0, tmp8, 8'b0, tmp8} */ + case MXU_OPTN3_PTN4: + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); + tcg_gen_deposit_tl(t0, t1, t1, 16, 16); + break; + /* XRa = {tmp8, 8'b0, tmp8, 8'b0} */ + case MXU_OPTN3_PTN5: + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); + tcg_gen_shli_tl(t1, t1, 8); + tcg_gen_deposit_tl(t0, t1, t1, 16, 16); + break; + /* XRa = {{8{sign of tmp8}}, tmp8, {8{sign of tmp8}}, tmp8} */ + case MXU_OPTN3_PTN6: + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_SB); + tcg_gen_mov_tl(t0, t1); + tcg_gen_andi_tl(t0, t0, 0xFF00FFFF); + tcg_gen_shli_tl(t1, t1, 16); + tcg_gen_or_tl(t0, t0, t1); + break; + /* XRa = {tmp8, tmp8, tmp8, tmp8} */ + case MXU_OPTN3_PTN7: + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); + tcg_gen_deposit_tl(t1, t1, t1, 8, 8); + tcg_gen_deposit_tl(t0, t1, t1, 16, 16); + break; + } + + gen_store_mxu_gpr(t0, XRa); + + gen_set_label(l0); + + tcg_temp_free(t0); + tcg_temp_free(t1); +} + /* * Decoding engine for MXU @@ -25134,9 +25220,7 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx) generate_exception_end(ctx, EXCP_RI); break; case OPC_MXU_S8LDD: - /* TODO: Implement emulation of S8LDD instruction. */ - MIPS_INVAL("OPC_MXU_S8LDD"); - generate_exception_end(ctx, EXCP_RI); + gen_mxu_s8ldd(ctx); break; case OPC_MXU_S8STD: /* TODO: Implement emulation of S8STD instruction. */ From patchwork Mon Oct 29 15:20:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 990318 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42kJdT6T2vz9s55 for ; Tue, 30 Oct 2018 02:37:49 +1100 (AEDT) Received: from localhost ([::1]:46303 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9bv-0006eA-1n for incoming@patchwork.ozlabs.org; Mon, 29 Oct 2018 11:37:47 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34404) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9Lg-0008Ss-EU for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:21:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gH9Lc-0003QB-FS for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:21:00 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:39510 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gH9Lb-0003IB-Sb for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:20:56 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id B03521A23D8; Mon, 29 Oct 2018 16:20:25 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 89C021A23B5; Mon, 29 Oct 2018 16:20:25 +0100 (CET) From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Mon, 29 Oct 2018 16:20:07 +0100 Message-Id: <1540826418-5501-17-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL 16/27] target/mips: Add emulation of MXU instruction D16MUL X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Craig Janeczek Add support for emulating the D16MUL MXU instruction. Reviewed-by: Aleksandar Markovic Signed-off-by: Craig Janeczek Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 66 ++++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 63 insertions(+), 3 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index cb7a24b..dbcb69b 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -24175,6 +24175,68 @@ static void gen_mxu_s8ldd(DisasContext *ctx) tcg_temp_free(t1); } +/* + * D16MUL XRa, XRb, XRc, XRd, optn2 - Signed 16 bit pattern multiplication + */ +static void gen_mxu_d16mul(DisasContext *ctx) +{ + TCGv t0, t1, t2, t3; + TCGLabel *l0; + uint32_t XRa, XRb, XRc, XRd, optn2; + + t0 = tcg_temp_new(); + t1 = tcg_temp_new(); + t2 = tcg_temp_new(); + t3 = tcg_temp_new(); + + l0 = gen_new_label(); + + XRa = extract32(ctx->opcode, 6, 4); + XRb = extract32(ctx->opcode, 10, 4); + XRc = extract32(ctx->opcode, 14, 4); + XRd = extract32(ctx->opcode, 18, 4); + optn2 = extract32(ctx->opcode, 22, 2); + + gen_load_mxu_cr(t0); + tcg_gen_andi_tl(t0, t0, MXU_CR_MXU_EN); + tcg_gen_brcondi_tl(TCG_COND_NE, t0, MXU_CR_MXU_EN, l0); + + gen_load_mxu_gpr(t1, XRb); + tcg_gen_sextract_tl(t0, t1, 0, 16); + tcg_gen_sextract_tl(t1, t1, 16, 16); + gen_load_mxu_gpr(t3, XRc); + tcg_gen_sextract_tl(t2, t3, 0, 16); + tcg_gen_sextract_tl(t3, t3, 16, 16); + + switch (optn2) { + case MXU_OPTN2_WW: /* XRB.H*XRC.H == lop, XRB.L*XRC.L == rop */ + tcg_gen_mul_tl(t3, t1, t3); + tcg_gen_mul_tl(t2, t0, t2); + break; + case MXU_OPTN2_LW: /* XRB.L*XRC.H == lop, XRB.L*XRC.L == rop */ + tcg_gen_mul_tl(t3, t0, t3); + tcg_gen_mul_tl(t2, t0, t2); + break; + case MXU_OPTN2_HW: /* XRB.H*XRC.H == lop, XRB.H*XRC.L == rop */ + tcg_gen_mul_tl(t3, t1, t3); + tcg_gen_mul_tl(t2, t1, t2); + break; + case MXU_OPTN2_XW: /* XRB.L*XRC.H == lop, XRB.H*XRC.L == rop */ + tcg_gen_mul_tl(t3, t0, t3); + tcg_gen_mul_tl(t2, t1, t2); + break; + } + gen_store_mxu_gpr(t3, XRa); + gen_store_mxu_gpr(t2, XRd); + + gen_set_label(l0); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(t2); + tcg_temp_free(t3); +} + /* * Decoding engine for MXU @@ -25139,9 +25201,7 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx) decode_opc_mxu__pool02(env, ctx); break; case OPC_MXU_D16MUL: - /* TODO: Implement emulation of D16MUL instruction. */ - MIPS_INVAL("OPC_MXU_D16MUL"); - generate_exception_end(ctx, EXCP_RI); + gen_mxu_d16mul(ctx); break; case OPC_MXU__POOL03: decode_opc_mxu__pool03(env, ctx); From patchwork Mon Oct 29 15:20:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 990311 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42kJWC3pQ7z9s55 for ; Tue, 30 Oct 2018 02:32:23 +1100 (AEDT) Received: from localhost ([::1]:46276 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9We-0002Rw-Mp for incoming@patchwork.ozlabs.org; Mon, 29 Oct 2018 11:32:20 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34411) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9Lg-0008Sw-F4 for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:21:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gH9Lb-0003P6-Fd for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:21:00 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:39519 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gH9LZ-0003IF-FG for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:20:55 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id C5F6D1A2289; Mon, 29 Oct 2018 16:20:25 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 931871A2254; Mon, 29 Oct 2018 16:20:25 +0100 (CET) From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Mon, 29 Oct 2018 16:20:08 +0100 Message-Id: <1540826418-5501-18-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL 17/27] target/mips: Add emulation of MXU instruction D16MAC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Craig Janeczek Add support for emulating the D16MAC MXU instruction. Reviewed-by: Aleksandar Markovic Signed-off-by: Craig Janeczek Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 90 +++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 87 insertions(+), 3 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index dbcb69b..4777228 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -24237,6 +24237,92 @@ static void gen_mxu_d16mul(DisasContext *ctx) tcg_temp_free(t3); } +/* + * D16MAC XRa, XRb, XRc, XRd, aptn2, optn2 - Signed 16 bit pattern multiply + * and accumulate + */ +static void gen_mxu_d16mac(DisasContext *ctx) +{ + TCGv t0, t1, t2, t3; + TCGLabel *l0; + uint32_t XRa, XRb, XRc, XRd, optn2, aptn2; + + t0 = tcg_temp_new(); + t1 = tcg_temp_new(); + t2 = tcg_temp_new(); + t3 = tcg_temp_new(); + + l0 = gen_new_label(); + + XRa = extract32(ctx->opcode, 6, 4); + XRb = extract32(ctx->opcode, 10, 4); + XRc = extract32(ctx->opcode, 14, 4); + XRd = extract32(ctx->opcode, 18, 4); + optn2 = extract32(ctx->opcode, 22, 2); + aptn2 = extract32(ctx->opcode, 24, 2); + + gen_load_mxu_cr(t0); + tcg_gen_andi_tl(t0, t0, MXU_CR_MXU_EN); + tcg_gen_brcondi_tl(TCG_COND_NE, t0, MXU_CR_MXU_EN, l0); + + gen_load_mxu_gpr(t1, XRb); + tcg_gen_sextract_tl(t0, t1, 0, 16); + tcg_gen_sextract_tl(t1, t1, 16, 16); + + gen_load_mxu_gpr(t3, XRc); + tcg_gen_sextract_tl(t2, t3, 0, 16); + tcg_gen_sextract_tl(t3, t3, 16, 16); + + switch (optn2) { + case MXU_OPTN2_WW: /* XRB.H*XRC.H == lop, XRB.L*XRC.L == rop */ + tcg_gen_mul_tl(t3, t1, t3); + tcg_gen_mul_tl(t2, t0, t2); + break; + case MXU_OPTN2_LW: /* XRB.L*XRC.H == lop, XRB.L*XRC.L == rop */ + tcg_gen_mul_tl(t3, t0, t3); + tcg_gen_mul_tl(t2, t0, t2); + break; + case MXU_OPTN2_HW: /* XRB.H*XRC.H == lop, XRB.H*XRC.L == rop */ + tcg_gen_mul_tl(t3, t1, t3); + tcg_gen_mul_tl(t2, t1, t2); + break; + case MXU_OPTN2_XW: /* XRB.L*XRC.H == lop, XRB.H*XRC.L == rop */ + tcg_gen_mul_tl(t3, t0, t3); + tcg_gen_mul_tl(t2, t1, t2); + break; + } + gen_load_mxu_gpr(t0, XRa); + gen_load_mxu_gpr(t1, XRd); + + switch (aptn2) { + case MXU_APTN2_AA: + tcg_gen_add_tl(t3, t0, t3); + tcg_gen_add_tl(t2, t1, t2); + break; + case MXU_APTN2_AS: + tcg_gen_add_tl(t3, t0, t3); + tcg_gen_sub_tl(t2, t1, t2); + break; + case MXU_APTN2_SA: + tcg_gen_sub_tl(t3, t0, t3); + tcg_gen_add_tl(t2, t1, t2); + break; + case MXU_APTN2_SS: + tcg_gen_sub_tl(t3, t0, t3); + tcg_gen_sub_tl(t2, t1, t2); + break; + } + gen_store_mxu_gpr(t3, XRa); + gen_store_mxu_gpr(t2, XRd); + + gen_set_label(l0); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(t2); + tcg_temp_free(t3); +} + /* * Decoding engine for MXU @@ -25207,9 +25293,7 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx) decode_opc_mxu__pool03(env, ctx); break; case OPC_MXU_D16MAC: - /* TODO: Implement emulation of D16MAC instruction. */ - MIPS_INVAL("OPC_MXU_D16MAC"); - generate_exception_end(ctx, EXCP_RI); + gen_mxu_d16mac(ctx); break; case OPC_MXU_D16MACF: /* TODO: Implement emulation of D16MACF instruction. */ From patchwork Mon Oct 29 15:20:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 990321 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42kJhr0h02z9s3Z for ; Tue, 30 Oct 2018 02:40:44 +1100 (AEDT) Received: from localhost ([::1]:46321 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9ej-0000gq-N5 for incoming@patchwork.ozlabs.org; Mon, 29 Oct 2018 11:40:41 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34400) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9Lg-0008Sq-EF for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:21:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gH9Lc-0003Py-Cl for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:21:00 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:39520 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gH9Lb-0003IH-Ma for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:20:56 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id D27131A23FB; Mon, 29 Oct 2018 16:20:25 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 9FCCF1A23C3; Mon, 29 Oct 2018 16:20:25 +0100 (CET) From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Mon, 29 Oct 2018 16:20:09 +0100 Message-Id: <1540826418-5501-19-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL 18/27] target/mips: Add emulation of MXU instructions Q8MUL and Q8MULSU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Craig Janeczek Adds support for emulating the Q8MUL and Q8MULSU MXU instructions. Reviewed-by: Aleksandar Markovic Signed-off-by: Craig Janeczek Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 101 ++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 94 insertions(+), 7 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 4777228..cc428be 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -24323,6 +24323,99 @@ static void gen_mxu_d16mac(DisasContext *ctx) tcg_temp_free(t3); } +/* + * Q8MUL XRa, XRb, XRc, XRd - Parallel unsigned 8 bit pattern multiply + * Q8MULSU XRa, XRb, XRc, XRd - Parallel signed 8 bit pattern multiply + */ +static void gen_mxu_q8mul_q8mulsu(DisasContext *ctx) +{ + TCGv t0, t1, t2, t3, t4, t5, t6, t7; + TCGLabel *l0; + uint32_t XRa, XRb, XRc, XRd, sel; + + t0 = tcg_temp_new(); + t1 = tcg_temp_new(); + t2 = tcg_temp_new(); + t3 = tcg_temp_new(); + t4 = tcg_temp_new(); + t5 = tcg_temp_new(); + t6 = tcg_temp_new(); + t7 = tcg_temp_new(); + + l0 = gen_new_label(); + + XRa = extract32(ctx->opcode, 6, 4); + XRb = extract32(ctx->opcode, 10, 4); + XRc = extract32(ctx->opcode, 14, 4); + XRd = extract32(ctx->opcode, 18, 4); + sel = extract32(ctx->opcode, 22, 2); + + gen_load_mxu_cr(t0); + tcg_gen_andi_tl(t0, t0, MXU_CR_MXU_EN); + tcg_gen_brcondi_tl(TCG_COND_NE, t0, MXU_CR_MXU_EN, l0); + + gen_load_mxu_gpr(t3, XRb); + gen_load_mxu_gpr(t7, XRc); + + if (sel == 0x2) { + /* Q8MULSU */ + tcg_gen_ext8s_tl(t0, t3); + tcg_gen_shri_tl(t3, t3, 8); + tcg_gen_ext8s_tl(t1, t3); + tcg_gen_shri_tl(t3, t3, 8); + tcg_gen_ext8s_tl(t2, t3); + tcg_gen_shri_tl(t3, t3, 8); + tcg_gen_ext8s_tl(t3, t3); + } else { + /* Q8MUL */ + tcg_gen_ext8u_tl(t0, t3); + tcg_gen_shri_tl(t3, t3, 8); + tcg_gen_ext8u_tl(t1, t3); + tcg_gen_shri_tl(t3, t3, 8); + tcg_gen_ext8u_tl(t2, t3); + tcg_gen_shri_tl(t3, t3, 8); + tcg_gen_ext8u_tl(t3, t3); + } + + tcg_gen_ext8u_tl(t4, t7); + tcg_gen_shri_tl(t7, t7, 8); + tcg_gen_ext8u_tl(t5, t7); + tcg_gen_shri_tl(t7, t7, 8); + tcg_gen_ext8u_tl(t6, t7); + tcg_gen_shri_tl(t7, t7, 8); + tcg_gen_ext8u_tl(t7, t7); + + tcg_gen_mul_tl(t0, t0, t4); + tcg_gen_mul_tl(t1, t1, t5); + tcg_gen_mul_tl(t2, t2, t6); + tcg_gen_mul_tl(t3, t3, t7); + + tcg_gen_andi_tl(t0, t0, 0xFFFF); + tcg_gen_andi_tl(t1, t1, 0xFFFF); + tcg_gen_andi_tl(t2, t2, 0xFFFF); + tcg_gen_andi_tl(t3, t3, 0xFFFF); + + tcg_gen_shli_tl(t1, t1, 16); + tcg_gen_shli_tl(t3, t3, 16); + + tcg_gen_or_tl(t0, t0, t1); + tcg_gen_or_tl(t1, t2, t3); + + gen_store_mxu_gpr(t0, XRd); + gen_store_mxu_gpr(t1, XRa); + + gen_set_label(l0); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(t2); + tcg_temp_free(t3); + tcg_temp_free(t4); + tcg_temp_free(t5); + tcg_temp_free(t6); + tcg_temp_free(t7); +} + /* * Decoding engine for MXU @@ -25114,14 +25207,8 @@ static void decode_opc_mxu__pool18(CPUMIPSState *env, DisasContext *ctx) switch (opcode) { case OPC_MXU_Q8MUL: - /* TODO: Implement emulation of Q8MUL instruction. */ - MIPS_INVAL("OPC_MXU_Q8MUL"); - generate_exception_end(ctx, EXCP_RI); - break; case OPC_MXU_Q8MULSU: - /* TODO: Implement emulation of Q8MULSU instruction. */ - MIPS_INVAL("OPC_MXU_Q8MULSU"); - generate_exception_end(ctx, EXCP_RI); + gen_mxu_q8mul_q8mulsu(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); From patchwork Mon Oct 29 15:20:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 990325 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42kJmB4FcBz9s3Z for ; Tue, 30 Oct 2018 02:43:38 +1100 (AEDT) Received: from localhost ([::1]:46336 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9hY-0004sp-6P for incoming@patchwork.ozlabs.org; Mon, 29 Oct 2018 11:43:36 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34430) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9Lh-0008Sy-2s for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:21:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gH9Lc-0003QM-G7 for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:21:00 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:39524 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gH9Lb-0003IJ-Tr for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:20:56 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id DA0831A2408; Mon, 29 Oct 2018 16:20:25 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id AA94A1A23CF; Mon, 29 Oct 2018 16:20:25 +0100 (CET) From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Mon, 29 Oct 2018 16:20:10 +0100 Message-Id: <1540826418-5501-20-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL 19/27] target/mips: Add emulation of MXU instructions S32LDD and S32LDDR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Craig Janeczek Add support for emulating the S32LDD and S32LDDR MXU instructions. Reviewed-by: Aleksandar Markovic Signed-off-by: Craig Janeczek Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 54 ++++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 47 insertions(+), 7 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index cc428be..15027b1 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -24416,6 +24416,52 @@ static void gen_mxu_q8mul_q8mulsu(DisasContext *ctx) tcg_temp_free(t7); } +/* + * S32LDD XRa, Rb, S12 - Load a word from memory to XRF + * S32LDDR XRa, Rb, S12 - Load a word from memory to XRF, reversed byte seq. + */ +static void gen_mxu_s32ldd_s32lddr(DisasContext *ctx) +{ + TCGv t0, t1; + TCGLabel *l0; + uint32_t XRa, Rb, s12, sel; + + t0 = tcg_temp_new(); + t1 = tcg_temp_new(); + + l0 = gen_new_label(); + + XRa = extract32(ctx->opcode, 6, 4); + s12 = extract32(ctx->opcode, 10, 10); + sel = extract32(ctx->opcode, 20, 1); + Rb = extract32(ctx->opcode, 21, 5); + + gen_load_mxu_cr(t0); + tcg_gen_andi_tl(t0, t0, MXU_CR_MXU_EN); + tcg_gen_brcondi_tl(TCG_COND_NE, t0, MXU_CR_MXU_EN, l0); + + gen_load_gpr(t0, Rb); + + tcg_gen_movi_tl(t1, s12); + tcg_gen_shli_tl(t1, t1, 2); + if (s12 & 0x200) { + tcg_gen_ori_tl(t1, t1, 0xFFFFF000); + } + tcg_gen_add_tl(t1, t0, t1); + tcg_gen_qemu_ld_tl(t1, t1, ctx->mem_idx, MO_SL); + + if (sel == 1) { + /* S32LDDR */ + tcg_gen_bswap32_tl(t1, t1); + } + gen_store_mxu_gpr(t1, XRa); + + gen_set_label(l0); + + tcg_temp_free(t0); + tcg_temp_free(t1); +} + /* * Decoding engine for MXU @@ -24645,14 +24691,8 @@ static void decode_opc_mxu__pool04(CPUMIPSState *env, DisasContext *ctx) switch (opcode) { case OPC_MXU_S32LDD: - /* TODO: Implement emulation of S32LDD instruction. */ - MIPS_INVAL("OPC_MXU_S32LDD"); - generate_exception_end(ctx, EXCP_RI); - break; case OPC_MXU_S32LDDR: - /* TODO: Implement emulation of S32LDDR instruction. */ - MIPS_INVAL("OPC_MXU_S32LDDR"); - generate_exception_end(ctx, EXCP_RI); + gen_mxu_s32ldd_s32lddr(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); From patchwork Mon Oct 29 15:20:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 990326 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42kJpD6SBJz9s3Z for ; Tue, 30 Oct 2018 02:45:23 +1100 (AEDT) Received: from localhost ([::1]:46343 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9jE-0008Fo-0V for incoming@patchwork.ozlabs.org; Mon, 29 Oct 2018 11:45:20 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34524) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9Lj-0008VL-Nl for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:21:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gH9Le-0003RW-48 for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:21:03 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:39620 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gH9Ld-0003JT-Hz for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:20:58 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 097931A23E0; Mon, 29 Oct 2018 16:20:26 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id B4C0A1A23DB; Mon, 29 Oct 2018 16:20:25 +0100 (CET) From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Mon, 29 Oct 2018 16:20:11 +0100 Message-Id: <1540826418-5501-21-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL 20/27] target/mips: Move MXU_EN check one level higher X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Aleksandar Markovic Move MXU_EN check to the main MXU decoding function, to avoid code repetition. Reviewed-by: Stefan Markovic Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 509 ++++++++++++++++++++++-------------------------- 1 file changed, 238 insertions(+), 271 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 15027b1..280b489 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -24095,23 +24095,16 @@ static void gen_mxu_s32m2i(DisasContext *ctx) static void gen_mxu_s8ldd(DisasContext *ctx) { TCGv t0, t1; - TCGLabel *l0; uint32_t XRa, Rb, s8, optn3; t0 = tcg_temp_new(); t1 = tcg_temp_new(); - l0 = gen_new_label(); - XRa = extract32(ctx->opcode, 6, 4); s8 = extract32(ctx->opcode, 10, 8); optn3 = extract32(ctx->opcode, 18, 3); Rb = extract32(ctx->opcode, 21, 5); - gen_load_mxu_cr(t0); - tcg_gen_andi_tl(t0, t0, MXU_CR_MXU_EN); - tcg_gen_brcondi_tl(TCG_COND_NE, t0, MXU_CR_MXU_EN, l0); - gen_load_gpr(t0, Rb); tcg_gen_addi_tl(t0, t0, (int8_t)s8); @@ -24169,8 +24162,6 @@ static void gen_mxu_s8ldd(DisasContext *ctx) gen_store_mxu_gpr(t0, XRa); - gen_set_label(l0); - tcg_temp_free(t0); tcg_temp_free(t1); } @@ -24181,7 +24172,6 @@ static void gen_mxu_s8ldd(DisasContext *ctx) static void gen_mxu_d16mul(DisasContext *ctx) { TCGv t0, t1, t2, t3; - TCGLabel *l0; uint32_t XRa, XRb, XRc, XRd, optn2; t0 = tcg_temp_new(); @@ -24189,18 +24179,12 @@ static void gen_mxu_d16mul(DisasContext *ctx) t2 = tcg_temp_new(); t3 = tcg_temp_new(); - l0 = gen_new_label(); - XRa = extract32(ctx->opcode, 6, 4); XRb = extract32(ctx->opcode, 10, 4); XRc = extract32(ctx->opcode, 14, 4); XRd = extract32(ctx->opcode, 18, 4); optn2 = extract32(ctx->opcode, 22, 2); - gen_load_mxu_cr(t0); - tcg_gen_andi_tl(t0, t0, MXU_CR_MXU_EN); - tcg_gen_brcondi_tl(TCG_COND_NE, t0, MXU_CR_MXU_EN, l0); - gen_load_mxu_gpr(t1, XRb); tcg_gen_sextract_tl(t0, t1, 0, 16); tcg_gen_sextract_tl(t1, t1, 16, 16); @@ -24229,8 +24213,6 @@ static void gen_mxu_d16mul(DisasContext *ctx) gen_store_mxu_gpr(t3, XRa); gen_store_mxu_gpr(t2, XRd); - gen_set_label(l0); - tcg_temp_free(t0); tcg_temp_free(t1); tcg_temp_free(t2); @@ -24244,7 +24226,6 @@ static void gen_mxu_d16mul(DisasContext *ctx) static void gen_mxu_d16mac(DisasContext *ctx) { TCGv t0, t1, t2, t3; - TCGLabel *l0; uint32_t XRa, XRb, XRc, XRd, optn2, aptn2; t0 = tcg_temp_new(); @@ -24252,8 +24233,6 @@ static void gen_mxu_d16mac(DisasContext *ctx) t2 = tcg_temp_new(); t3 = tcg_temp_new(); - l0 = gen_new_label(); - XRa = extract32(ctx->opcode, 6, 4); XRb = extract32(ctx->opcode, 10, 4); XRc = extract32(ctx->opcode, 14, 4); @@ -24261,10 +24240,6 @@ static void gen_mxu_d16mac(DisasContext *ctx) optn2 = extract32(ctx->opcode, 22, 2); aptn2 = extract32(ctx->opcode, 24, 2); - gen_load_mxu_cr(t0); - tcg_gen_andi_tl(t0, t0, MXU_CR_MXU_EN); - tcg_gen_brcondi_tl(TCG_COND_NE, t0, MXU_CR_MXU_EN, l0); - gen_load_mxu_gpr(t1, XRb); tcg_gen_sextract_tl(t0, t1, 0, 16); tcg_gen_sextract_tl(t1, t1, 16, 16); @@ -24315,8 +24290,6 @@ static void gen_mxu_d16mac(DisasContext *ctx) gen_store_mxu_gpr(t3, XRa); gen_store_mxu_gpr(t2, XRd); - gen_set_label(l0); - tcg_temp_free(t0); tcg_temp_free(t1); tcg_temp_free(t2); @@ -24330,7 +24303,6 @@ static void gen_mxu_d16mac(DisasContext *ctx) static void gen_mxu_q8mul_q8mulsu(DisasContext *ctx) { TCGv t0, t1, t2, t3, t4, t5, t6, t7; - TCGLabel *l0; uint32_t XRa, XRb, XRc, XRd, sel; t0 = tcg_temp_new(); @@ -24342,18 +24314,12 @@ static void gen_mxu_q8mul_q8mulsu(DisasContext *ctx) t6 = tcg_temp_new(); t7 = tcg_temp_new(); - l0 = gen_new_label(); - XRa = extract32(ctx->opcode, 6, 4); XRb = extract32(ctx->opcode, 10, 4); XRc = extract32(ctx->opcode, 14, 4); XRd = extract32(ctx->opcode, 18, 4); sel = extract32(ctx->opcode, 22, 2); - gen_load_mxu_cr(t0); - tcg_gen_andi_tl(t0, t0, MXU_CR_MXU_EN); - tcg_gen_brcondi_tl(TCG_COND_NE, t0, MXU_CR_MXU_EN, l0); - gen_load_mxu_gpr(t3, XRb); gen_load_mxu_gpr(t7, XRc); @@ -24404,8 +24370,6 @@ static void gen_mxu_q8mul_q8mulsu(DisasContext *ctx) gen_store_mxu_gpr(t0, XRd); gen_store_mxu_gpr(t1, XRa); - gen_set_label(l0); - tcg_temp_free(t0); tcg_temp_free(t1); tcg_temp_free(t2); @@ -24423,23 +24387,16 @@ static void gen_mxu_q8mul_q8mulsu(DisasContext *ctx) static void gen_mxu_s32ldd_s32lddr(DisasContext *ctx) { TCGv t0, t1; - TCGLabel *l0; uint32_t XRa, Rb, s12, sel; t0 = tcg_temp_new(); t1 = tcg_temp_new(); - l0 = gen_new_label(); - XRa = extract32(ctx->opcode, 6, 4); s12 = extract32(ctx->opcode, 10, 10); sel = extract32(ctx->opcode, 20, 1); Rb = extract32(ctx->opcode, 21, 5); - gen_load_mxu_cr(t0); - tcg_gen_andi_tl(t0, t0, MXU_CR_MXU_EN); - tcg_gen_brcondi_tl(TCG_COND_NE, t0, MXU_CR_MXU_EN, l0); - gen_load_gpr(t0, Rb); tcg_gen_movi_tl(t1, s12); @@ -24456,8 +24413,6 @@ static void gen_mxu_s32ldd_s32lddr(DisasContext *ctx) } gen_store_mxu_gpr(t1, XRa); - gen_set_label(l0); - tcg_temp_free(t0); tcg_temp_free(t1); } @@ -25383,232 +25338,244 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx) return; } - switch (opcode) { - case OPC_MXU_S32MADD: - /* TODO: Implement emulation of S32MADD instruction. */ - MIPS_INVAL("OPC_MXU_S32MADD"); - generate_exception_end(ctx, EXCP_RI); - break; - case OPC_MXU_S32MADDU: - /* TODO: Implement emulation of S32MADDU instruction. */ - MIPS_INVAL("OPC_MXU_S32MADDU"); - generate_exception_end(ctx, EXCP_RI); - break; - case OPC_MXU__POOL00: - decode_opc_mxu__pool00(env, ctx); - break; - case OPC_MXU_S32MSUB: - /* TODO: Implement emulation of S32MSUB instruction. */ - MIPS_INVAL("OPC_MXU_S32MSUB"); - generate_exception_end(ctx, EXCP_RI); - break; - case OPC_MXU_S32MSUBU: - /* TODO: Implement emulation of S32MSUBU instruction. */ - MIPS_INVAL("OPC_MXU_S32MSUBU"); - generate_exception_end(ctx, EXCP_RI); - break; - case OPC_MXU__POOL01: - decode_opc_mxu__pool01(env, ctx); - break; - case OPC_MXU__POOL02: - decode_opc_mxu__pool02(env, ctx); - break; - case OPC_MXU_D16MUL: - gen_mxu_d16mul(ctx); - break; - case OPC_MXU__POOL03: - decode_opc_mxu__pool03(env, ctx); - break; - case OPC_MXU_D16MAC: - gen_mxu_d16mac(ctx); - break; - case OPC_MXU_D16MACF: - /* TODO: Implement emulation of D16MACF instruction. */ - MIPS_INVAL("OPC_MXU_D16MACF"); - generate_exception_end(ctx, EXCP_RI); - break; - case OPC_MXU_D16MADL: - /* TODO: Implement emulation of D16MADL instruction. */ - MIPS_INVAL("OPC_MXU_D16MADL"); - generate_exception_end(ctx, EXCP_RI); - break; - case OPC_MXU_S16MAD: - /* TODO: Implement emulation of S16MAD instruction. */ - MIPS_INVAL("OPC_MXU_S16MAD"); - generate_exception_end(ctx, EXCP_RI); - break; - case OPC_MXU_Q16ADD: - /* TODO: Implement emulation of Q16ADD instruction. */ - MIPS_INVAL("OPC_MXU_Q16ADD"); - generate_exception_end(ctx, EXCP_RI); - break; - case OPC_MXU_D16MACE: - /* TODO: Implement emulation of D16MACE instruction. */ - MIPS_INVAL("OPC_MXU_D16MACE"); - generate_exception_end(ctx, EXCP_RI); - break; - case OPC_MXU__POOL04: - decode_opc_mxu__pool04(env, ctx); - break; - case OPC_MXU__POOL05: - decode_opc_mxu__pool05(env, ctx); - break; - case OPC_MXU__POOL06: - decode_opc_mxu__pool06(env, ctx); - break; - case OPC_MXU__POOL07: - decode_opc_mxu__pool07(env, ctx); - break; - case OPC_MXU__POOL08: - decode_opc_mxu__pool08(env, ctx); - break; - case OPC_MXU__POOL09: - decode_opc_mxu__pool09(env, ctx); - break; - case OPC_MXU__POOL10: - decode_opc_mxu__pool10(env, ctx); - break; - case OPC_MXU__POOL11: - decode_opc_mxu__pool11(env, ctx); - break; - case OPC_MXU_D32ADD: - /* TODO: Implement emulation of D32ADD instruction. */ - MIPS_INVAL("OPC_MXU_D32ADD"); - generate_exception_end(ctx, EXCP_RI); - break; - case OPC_MXU__POOL12: - decode_opc_mxu__pool12(env, ctx); - break; - case OPC_MXU__POOL13: - decode_opc_mxu__pool13(env, ctx); - break; - case OPC_MXU__POOL14: - decode_opc_mxu__pool14(env, ctx); - break; - case OPC_MXU_Q8ACCE: - /* TODO: Implement emulation of Q8ACCE instruction. */ - MIPS_INVAL("OPC_MXU_Q8ACCE"); - generate_exception_end(ctx, EXCP_RI); - break; - case OPC_MXU_S8LDD: - gen_mxu_s8ldd(ctx); - break; - case OPC_MXU_S8STD: - /* TODO: Implement emulation of S8STD instruction. */ - MIPS_INVAL("OPC_MXU_S8STD"); - generate_exception_end(ctx, EXCP_RI); - break; - case OPC_MXU_S8LDI: - /* TODO: Implement emulation of S8LDI instruction. */ - MIPS_INVAL("OPC_MXU_S8LDI"); - generate_exception_end(ctx, EXCP_RI); - break; - case OPC_MXU_S8SDI: - /* TODO: Implement emulation of S8SDI instruction. */ - MIPS_INVAL("OPC_MXU_S8SDI"); - generate_exception_end(ctx, EXCP_RI); - break; - case OPC_MXU__POOL15: - decode_opc_mxu__pool15(env, ctx); - break; - case OPC_MXU__POOL16: - decode_opc_mxu__pool16(env, ctx); - break; - case OPC_MXU_LXB: - /* TODO: Implement emulation of LXB instruction. */ - MIPS_INVAL("OPC_MXU_LXB"); - generate_exception_end(ctx, EXCP_RI); - break; - case OPC_MXU_S16LDD: - /* TODO: Implement emulation of S16LDD instruction. */ - MIPS_INVAL("OPC_MXU_S16LDD"); - generate_exception_end(ctx, EXCP_RI); - break; - case OPC_MXU_S16STD: - /* TODO: Implement emulation of S16STD instruction. */ - MIPS_INVAL("OPC_MXU_S16STD"); - generate_exception_end(ctx, EXCP_RI); - break; - case OPC_MXU_S16LDI: - /* TODO: Implement emulation of S16LDI instruction. */ - MIPS_INVAL("OPC_MXU_S16LDI"); - generate_exception_end(ctx, EXCP_RI); - break; - case OPC_MXU_S16SDI: - /* TODO: Implement emulation of S16SDI instruction. */ - MIPS_INVAL("OPC_MXU_S16SDI"); - generate_exception_end(ctx, EXCP_RI); - break; - case OPC_MXU_D32SLL: - /* TODO: Implement emulation of D32SLL instruction. */ - MIPS_INVAL("OPC_MXU_D32SLL"); - generate_exception_end(ctx, EXCP_RI); - break; - case OPC_MXU_D32SLR: - /* TODO: Implement emulation of D32SLR instruction. */ - MIPS_INVAL("OPC_MXU_D32SLR"); - generate_exception_end(ctx, EXCP_RI); - break; - case OPC_MXU_D32SARL: - /* TODO: Implement emulation of D32SARL instruction. */ - MIPS_INVAL("OPC_MXU_D32SARL"); - generate_exception_end(ctx, EXCP_RI); - break; - case OPC_MXU_D32SAR: - /* TODO: Implement emulation of D32SAR instruction. */ - MIPS_INVAL("OPC_MXU_D32SAR"); - generate_exception_end(ctx, EXCP_RI); - break; - case OPC_MXU_Q16SLL: - /* TODO: Implement emulation of Q16SLL instruction. */ - MIPS_INVAL("OPC_MXU_Q16SLL"); - generate_exception_end(ctx, EXCP_RI); - break; - case OPC_MXU_Q16SLR: - /* TODO: Implement emulation of Q16SLR instruction. */ - MIPS_INVAL("OPC_MXU_Q16SLR"); - generate_exception_end(ctx, EXCP_RI); - break; - case OPC_MXU__POOL17: - decode_opc_mxu__pool17(env, ctx); - break; - case OPC_MXU_Q16SAR: - /* TODO: Implement emulation of Q16SAR instruction. */ - MIPS_INVAL("OPC_MXU_Q16SAR"); - generate_exception_end(ctx, EXCP_RI); - break; - case OPC_MXU__POOL18: - decode_opc_mxu__pool18(env, ctx); - break; - case OPC_MXU__POOL19: - decode_opc_mxu__pool19(env, ctx); - break; - case OPC_MXU__POOL20: - decode_opc_mxu__pool20(env, ctx); - break; - case OPC_MXU_Q16SCOP: - /* TODO: Implement emulation of Q16SCOP instruction. */ - MIPS_INVAL("OPC_MXU_Q16SCOP"); - generate_exception_end(ctx, EXCP_RI); - break; - case OPC_MXU_Q8MADL: - /* TODO: Implement emulation of Q8MADL instruction. */ - MIPS_INVAL("OPC_MXU_Q8MADL"); - generate_exception_end(ctx, EXCP_RI); - break; - case OPC_MXU_S32SFL: - /* TODO: Implement emulation of S32SFL instruction. */ - MIPS_INVAL("OPC_MXU_S32SFL"); - generate_exception_end(ctx, EXCP_RI); - break; - case OPC_MXU_Q8SAD: - /* TODO: Implement emulation of Q8SAD instruction. */ - MIPS_INVAL("OPC_MXU_Q8SAD"); - generate_exception_end(ctx, EXCP_RI); - break; - default: - MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + { + TCGv t_mxu_cr = tcg_temp_new(); + TCGLabel *l_exit = gen_new_label(); + + gen_load_mxu_cr(t_mxu_cr); + tcg_gen_andi_tl(t_mxu_cr, t_mxu_cr, MXU_CR_MXU_EN); + tcg_gen_brcondi_tl(TCG_COND_NE, t_mxu_cr, MXU_CR_MXU_EN, l_exit); + + switch (opcode) { + case OPC_MXU_S32MADD: + /* TODO: Implement emulation of S32MADD instruction. */ + MIPS_INVAL("OPC_MXU_S32MADD"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_S32MADDU: + /* TODO: Implement emulation of S32MADDU instruction. */ + MIPS_INVAL("OPC_MXU_S32MADDU"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU__POOL00: + decode_opc_mxu__pool00(env, ctx); + break; + case OPC_MXU_S32MSUB: + /* TODO: Implement emulation of S32MSUB instruction. */ + MIPS_INVAL("OPC_MXU_S32MSUB"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_S32MSUBU: + /* TODO: Implement emulation of S32MSUBU instruction. */ + MIPS_INVAL("OPC_MXU_S32MSUBU"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU__POOL01: + decode_opc_mxu__pool01(env, ctx); + break; + case OPC_MXU__POOL02: + decode_opc_mxu__pool02(env, ctx); + break; + case OPC_MXU_D16MUL: + gen_mxu_d16mul(ctx); + break; + case OPC_MXU__POOL03: + decode_opc_mxu__pool03(env, ctx); + break; + case OPC_MXU_D16MAC: + gen_mxu_d16mac(ctx); + break; + case OPC_MXU_D16MACF: + /* TODO: Implement emulation of D16MACF instruction. */ + MIPS_INVAL("OPC_MXU_D16MACF"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_D16MADL: + /* TODO: Implement emulation of D16MADL instruction. */ + MIPS_INVAL("OPC_MXU_D16MADL"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_S16MAD: + /* TODO: Implement emulation of S16MAD instruction. */ + MIPS_INVAL("OPC_MXU_S16MAD"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_Q16ADD: + /* TODO: Implement emulation of Q16ADD instruction. */ + MIPS_INVAL("OPC_MXU_Q16ADD"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_D16MACE: + /* TODO: Implement emulation of D16MACE instruction. */ + MIPS_INVAL("OPC_MXU_D16MACE"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU__POOL04: + decode_opc_mxu__pool04(env, ctx); + break; + case OPC_MXU__POOL05: + decode_opc_mxu__pool05(env, ctx); + break; + case OPC_MXU__POOL06: + decode_opc_mxu__pool06(env, ctx); + break; + case OPC_MXU__POOL07: + decode_opc_mxu__pool07(env, ctx); + break; + case OPC_MXU__POOL08: + decode_opc_mxu__pool08(env, ctx); + break; + case OPC_MXU__POOL09: + decode_opc_mxu__pool09(env, ctx); + break; + case OPC_MXU__POOL10: + decode_opc_mxu__pool10(env, ctx); + break; + case OPC_MXU__POOL11: + decode_opc_mxu__pool11(env, ctx); + break; + case OPC_MXU_D32ADD: + /* TODO: Implement emulation of D32ADD instruction. */ + MIPS_INVAL("OPC_MXU_D32ADD"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU__POOL12: + decode_opc_mxu__pool12(env, ctx); + break; + case OPC_MXU__POOL13: + decode_opc_mxu__pool13(env, ctx); + break; + case OPC_MXU__POOL14: + decode_opc_mxu__pool14(env, ctx); + break; + case OPC_MXU_Q8ACCE: + /* TODO: Implement emulation of Q8ACCE instruction. */ + MIPS_INVAL("OPC_MXU_Q8ACCE"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_S8LDD: + gen_mxu_s8ldd(ctx); + break; + case OPC_MXU_S8STD: + /* TODO: Implement emulation of S8STD instruction. */ + MIPS_INVAL("OPC_MXU_S8STD"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_S8LDI: + /* TODO: Implement emulation of S8LDI instruction. */ + MIPS_INVAL("OPC_MXU_S8LDI"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_S8SDI: + /* TODO: Implement emulation of S8SDI instruction. */ + MIPS_INVAL("OPC_MXU_S8SDI"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU__POOL15: + decode_opc_mxu__pool15(env, ctx); + break; + case OPC_MXU__POOL16: + decode_opc_mxu__pool16(env, ctx); + break; + case OPC_MXU_LXB: + /* TODO: Implement emulation of LXB instruction. */ + MIPS_INVAL("OPC_MXU_LXB"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_S16LDD: + /* TODO: Implement emulation of S16LDD instruction. */ + MIPS_INVAL("OPC_MXU_S16LDD"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_S16STD: + /* TODO: Implement emulation of S16STD instruction. */ + MIPS_INVAL("OPC_MXU_S16STD"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_S16LDI: + /* TODO: Implement emulation of S16LDI instruction. */ + MIPS_INVAL("OPC_MXU_S16LDI"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_S16SDI: + /* TODO: Implement emulation of S16SDI instruction. */ + MIPS_INVAL("OPC_MXU_S16SDI"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_D32SLL: + /* TODO: Implement emulation of D32SLL instruction. */ + MIPS_INVAL("OPC_MXU_D32SLL"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_D32SLR: + /* TODO: Implement emulation of D32SLR instruction. */ + MIPS_INVAL("OPC_MXU_D32SLR"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_D32SARL: + /* TODO: Implement emulation of D32SARL instruction. */ + MIPS_INVAL("OPC_MXU_D32SARL"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_D32SAR: + /* TODO: Implement emulation of D32SAR instruction. */ + MIPS_INVAL("OPC_MXU_D32SAR"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_Q16SLL: + /* TODO: Implement emulation of Q16SLL instruction. */ + MIPS_INVAL("OPC_MXU_Q16SLL"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_Q16SLR: + /* TODO: Implement emulation of Q16SLR instruction. */ + MIPS_INVAL("OPC_MXU_Q16SLR"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU__POOL17: + decode_opc_mxu__pool17(env, ctx); + break; + case OPC_MXU_Q16SAR: + /* TODO: Implement emulation of Q16SAR instruction. */ + MIPS_INVAL("OPC_MXU_Q16SAR"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU__POOL18: + decode_opc_mxu__pool18(env, ctx); + break; + case OPC_MXU__POOL19: + decode_opc_mxu__pool19(env, ctx); + break; + case OPC_MXU__POOL20: + decode_opc_mxu__pool20(env, ctx); + break; + case OPC_MXU_Q16SCOP: + /* TODO: Implement emulation of Q16SCOP instruction. */ + MIPS_INVAL("OPC_MXU_Q16SCOP"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_Q8MADL: + /* TODO: Implement emulation of Q8MADL instruction. */ + MIPS_INVAL("OPC_MXU_Q8MADL"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_S32SFL: + /* TODO: Implement emulation of S32SFL instruction. */ + MIPS_INVAL("OPC_MXU_S32SFL"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_Q8SAD: + /* TODO: Implement emulation of Q8SAD instruction. */ + MIPS_INVAL("OPC_MXU_Q8SAD"); + generate_exception_end(ctx, EXCP_RI); + break; + default: + MIPS_INVAL("decode_opc_mxu"); + generate_exception_end(ctx, EXCP_RI); + } + + gen_set_label(l_exit); + tcg_temp_free(t_mxu_cr); } } From patchwork Mon Oct 29 15:20:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 990340 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42kJst5LxDz9s3Z for ; Tue, 30 Oct 2018 02:48:34 +1100 (AEDT) Received: from localhost ([::1]:46363 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9mK-0002Vy-9S for incoming@patchwork.ozlabs.org; Mon, 29 Oct 2018 11:48:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34474) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9Lh-0008TD-Tm for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:21:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gH9Lc-0003QS-HI for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:21:01 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:39526 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gH9Lc-0003IL-03 for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:20:56 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 023881A23DD; Mon, 29 Oct 2018 16:20:26 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id C62A21A23B5; Mon, 29 Oct 2018 16:20:25 +0100 (CET) From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Mon, 29 Oct 2018 16:20:12 +0100 Message-Id: <1540826418-5501-22-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL 21/27] target/mips: Amend MXU ASE overview note X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Aleksandar Markovic Add prefix, suffix, operation descriptions, and other corrections and amendments to the comment that describes MXU ASE. Reviewed-by: Stefan Markovic Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 84 +++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 74 insertions(+), 10 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 280b489..60320cb 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1410,25 +1410,89 @@ enum { * MXU unit contains 17 registers called X0-X16. X0 is always zero, and X16 is * the control register. * - * The notation used in MXU assembler mnemonics: + * The notation used in MXU assembler mnemonics + * -------------------------------------------- + * + * Registers: * * XRa, XRb, XRc, XRd - MXU registers * Rb, Rc, Rd, Rs, Rt - general purpose MIPS registers - * s12 - a subfield of an instruction code - * strd2 - a subfield of an instruction code - * eptn2 - a subfield of an instruction code - * eptn3 - a subfield of an instruction code - * optn2 - a subfield of an instruction code - * optn3 - a subfield of an instruction code - * sft4 - a subfield of an instruction code + * + * Subfields: + * + * aptn1 - 1-bit accumulate add/subtract pattern + * aptn2 - 2-bit accumulate add/subtract pattern + * eptn2 - 2-bit execute add/subtract pattern + * optn2 - 2-bit operand pattern + * optn3 - 3-bit operand pattern + * sft4 - 4-bit shift amount + * strd2 - 2-bit stride amount + * + * Prefixes: + * + * + * S 32 + * D 16 + * Q 8 + * + * Suffixes: + * + * E - Expand results + * F - Fixed point multiplication + * L - Low part result + * R - Doing rounding + * V - Variable instead of immediate + * W - Combine above L and V + * + * Operations: + * + * ADD - Add or subtract + * ADDC - Add with carry-in + * ACC - Accumulate + * ASUM - Sum together then accumulate (add or subtract) + * ASUMC - Sum together then accumulate (add or subtract) with carry-in + * AVG - Average between 2 operands + * ABD - Absolute difference + * ALN - Align data + * AND - Logical bitwise 'and' operation + * CPS - Copy sign + * EXTR - Extract bits + * I2M - Move from GPR register to MXU register + * LDD - Load data from memory to XRF + * LDI - Load data from memory to XRF (and increase the address base) + * LUI - Load unsigned immediate + * MUL - Multiply + * MULU - Unsigned multiply + * MADD - 64-bit operand add 32x32 product + * MSUB - 64-bit operand subtract 32x32 product + * MAC - Multiply and accumulate (add or subtract) + * MAD - Multiply and add or subtract + * MAX - Maximum between 2 operands + * MIN - Minimum between 2 operands + * M2I - Move from MXU register to GPR register + * MOVZ - Move if zero + * MOVN - Move if non-zero + * NOR - Logical bitwise 'nor' operation + * OR - Logical bitwise 'or' operation + * STD - Store data from XRF to memory + * SDI - Store data from XRF to memory (and increase the address base) + * SLT - Set of less than comparison + * SAD - Sum of absolute differences + * SLL - Logical shift left + * SLR - Logical shift right + * SAR - Arithmetic shift right + * SAT - Saturation + * SFL - Shuffle + * SCOP - Calculate x’s scope (-1, means x<0; 0, means x==0; 1, means x>0) + * XOR - Logical bitwise 'exclusive or' operation * * Load/Store instructions Multiplication instructions * ----------------------- --------------------------- * * S32LDD XRa, Rb, s12 S32MADD XRa, XRd, Rs, Rt * S32STD XRa, Rb, s12 S32MADDU XRa, XRd, Rs, Rt - * S32LDDV XRa, Rb, rc, strd2 S32SUB XRa, XRd, Rs, Rt - * S32STDV XRa, Rb, rc, strd2 S32SUBU XRa, XRd, Rs, Rt + * S32LDDV XRa, Rb, rc, strd2 S32MSUB XRa, XRd, Rs, Rt + * S32STDV XRa, Rb, rc, strd2 S32MSUBU XRa, XRd, Rs, Rt * S32LDI XRa, Rb, s12 S32MUL XRa, XRd, Rs, Rt * S32SDI XRa, Rb, s12 S32MULU XRa, XRd, Rs, Rt * S32LDIV XRa, Rb, rc, strd2 D16MUL XRa, XRb, XRc, XRd, optn2 From patchwork Mon Oct 29 15:20:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 990307 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42kJRg4RJPz9s55 for ; Tue, 30 Oct 2018 02:29:18 +1100 (AEDT) Received: from localhost ([::1]:46259 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9Te-0008VI-5t for incoming@patchwork.ozlabs.org; Mon, 29 Oct 2018 11:29:14 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34410) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9Lg-0008Sv-Ex for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:21:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gH9Lb-0003PK-Q5 for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:21:00 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:39615 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gH9Lb-0003JP-FQ for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:20:55 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 0A8E31A2410; Mon, 29 Oct 2018 16:20:26 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id CF9CF1A23F1; Mon, 29 Oct 2018 16:20:25 +0100 (CET) From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Mon, 29 Oct 2018 16:20:13 +0100 Message-Id: <1540826418-5501-23-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL 22/27] elf: Define MIPS_ABI_FP_UNKNOWN macro X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Stefan Markovic Add MIPS_ABI_FP_UNKNOWN as QEMU internal value to represent unknown fp_abi (based on kernel mips/include/asm/elf.h definition) Reviewed-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- include/elf.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/elf.h b/include/elf.h index 5f45f9b..c151164 100644 --- a/include/elf.h +++ b/include/elf.h @@ -87,6 +87,8 @@ typedef int64_t Elf64_Sxword; #define EF_MIPS_MACH_LS3A 0x00a20000 /* ST Microelectronics Loongson 3A */ #define EF_MIPS_MACH 0x00ff0000 /* EF_MIPS_MACH_xxx selection mask */ +#define MIPS_ABI_FP_UNKNOWN (-1) /* Unknown FP ABI (internal) */ + #define MIPS_ABI_FP_ANY 0x0 /* FP ABI doesn't matter */ #define MIPS_ABI_FP_DOUBLE 0x1 /* -mdouble-float */ #define MIPS_ABI_FP_SINGLE 0x2 /* -msingle-float */ From patchwork Mon Oct 29 15:20:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 990348 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42kK5n583fz9s3Z for ; Tue, 30 Oct 2018 02:58:53 +1100 (AEDT) Received: from localhost ([::1]:46424 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9wJ-0004gZ-9g for incoming@patchwork.ozlabs.org; Mon, 29 Oct 2018 11:58:51 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34434) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9Lh-0008TC-7P for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:21:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gH9Ld-0003RM-OO for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:21:01 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:39619 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gH9Ld-0003JN-Ge for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:20:57 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 1FA771A23B5; Mon, 29 Oct 2018 16:20:26 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id DA07A1A23FC; Mon, 29 Oct 2018 16:20:25 +0100 (CET) From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Mon, 29 Oct 2018 16:20:14 +0100 Message-Id: <1540826418-5501-24-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL 23/27] linux-user: Extend image_info struct with MIPS fp_abi and interp_fp_abi fields X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Stefan Markovic Add MIPS specific image_info struct fields fp_abi and interp_fp_abi to store executable and interpreter fp_abi values (based on kernel struct arch_elf_state in mips/include/asm/elf.h). Reviewed-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- linux-user/qemu.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/linux-user/qemu.h b/linux-user/qemu.h index 1beb6a2..a752c1c 100644 --- a/linux-user/qemu.h +++ b/linux-user/qemu.h @@ -61,6 +61,10 @@ struct image_info { abi_ulong interpreter_loadmap_addr; abi_ulong interpreter_pt_dynamic_addr; struct image_info *other_info; +#ifdef TARGET_MIPS + int fp_abi; + int interp_fp_abi; +#endif }; #ifdef TARGET_I386 From patchwork Mon Oct 29 15:20:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 990314 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42kJYt5v7vz9s55 for ; Tue, 30 Oct 2018 02:34:41 +1100 (AEDT) Received: from localhost ([::1]:46284 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9Ys-00047B-O2 for incoming@patchwork.ozlabs.org; Mon, 29 Oct 2018 11:34:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34396) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9Lg-0008Sn-DW for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:21:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gH9Lc-0003QH-G2 for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:21:00 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:39618 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gH9Lb-0003JO-VL for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:20:56 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 2583C1A23C3; Mon, 29 Oct 2018 16:20:26 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id E4C041A2254; Mon, 29 Oct 2018 16:20:25 +0100 (CET) From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Mon, 29 Oct 2018 16:20:15 +0100 Message-Id: <1540826418-5501-25-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL 24/27] linux-user: Extract MIPS abiflags from ELF file X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Stefan Markovic Read MIPS.abiflags section from ELF file into Mips_elf_abiflags_v0 struct. Reviewed-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- linux-user/elfload.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 055f6a9..5881233 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -1517,11 +1517,25 @@ static void bswap_sym(struct elf_sym *sym) bswaptls(&sym->st_size); bswap16s(&sym->st_shndx); } + +#ifdef TARGET_MIPS +static void bswap_mips_abiflags(Mips_elf_abiflags_v0 *abiflags) +{ + bswap16s(&abiflags->version); + bswap32s(&abiflags->ases); + bswap32s(&abiflags->isa_ext); + bswap32s(&abiflags->flags1); + bswap32s(&abiflags->flags2); +} +#endif #else static inline void bswap_ehdr(struct elfhdr *ehdr) { } static inline void bswap_phdr(struct elf_phdr *phdr, int phnum) { } static inline void bswap_shdr(struct elf_shdr *shdr, int shnum) { } static inline void bswap_sym(struct elf_sym *sym) { } +#ifdef TARGET_MIPS +static inline void bswap_mips_abiflags(Mips_elf_abiflags_v0 *abiflags) { } +#endif #endif #ifdef USE_ELF_CORE_DUMP @@ -2364,6 +2378,25 @@ static void load_elf_image(const char *image_name, int image_fd, goto exit_errmsg; } *pinterp_name = interp_name; +#ifdef TARGET_MIPS + } else if (eppnt->p_type == PT_MIPS_ABIFLAGS) { + Mips_elf_abiflags_v0 abiflags; + if (eppnt->p_filesz < sizeof(Mips_elf_abiflags_v0)) { + errmsg = "Invalid PT_MIPS_ABIFLAGS entry"; + goto exit_errmsg; + } + if (eppnt->p_offset + eppnt->p_filesz <= BPRM_BUF_SIZE) { + memcpy(&abiflags, bprm_buf + eppnt->p_offset, + sizeof(Mips_elf_abiflags_v0)); + } else { + retval = pread(image_fd, &abiflags, sizeof(Mips_elf_abiflags_v0), + eppnt->p_offset); + if (retval != sizeof(Mips_elf_abiflags_v0)) { + goto exit_perror; + } + } + bswap_mips_abiflags(&abiflags); +#endif } } From patchwork Mon Oct 29 15:20:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 990324 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42kJlr5T6dz9s55 for ; Tue, 30 Oct 2018 02:43:20 +1100 (AEDT) Received: from localhost ([::1]:46334 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9hF-0003wZ-Mr for incoming@patchwork.ozlabs.org; Mon, 29 Oct 2018 11:43:17 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34398) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9Lg-0008So-E2 for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:21:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gH9Lc-0003Pv-Cm for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:21:00 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:39625 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gH9Lb-0003JX-Px for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:20:55 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 2ACF41A23DB; Mon, 29 Oct 2018 16:20:26 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id ED4481A23CF; Mon, 29 Oct 2018 16:20:25 +0100 (CET) From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Mon, 29 Oct 2018 16:20:16 +0100 Message-Id: <1540826418-5501-26-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL 25/27] linux-user: Read and set FP ABI value from MIPS abiflags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Stefan Markovic Set fp_abi and interp_fp_abi values to current fp_abi value read from MIPS.abiflags. Reviewed-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- linux-user/elfload.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 5881233..5bccd2e 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -2396,6 +2396,7 @@ static void load_elf_image(const char *image_name, int image_fd, } } bswap_mips_abiflags(&abiflags); + info->fp_abi = abiflags.fp_abi; #endif } } @@ -2708,6 +2709,9 @@ int load_elf_binary(struct linux_binprm *bprm, struct image_info *info) target_mmap(0, qemu_host_page_size, PROT_READ | PROT_EXEC, MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); } +#ifdef TARGET_MIPS + info->interp_fp_abi = interp_info.fp_abi; +#endif } bprm->p = create_elf_tables(bprm->p, bprm->argc, bprm->envc, &elf_ex, From patchwork Mon Oct 29 15:20:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 990343 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42kJyj1jBpz9s3Z for ; Tue, 30 Oct 2018 02:52:45 +1100 (AEDT) Received: from localhost ([::1]:46391 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9qM-0006iD-5B for incoming@patchwork.ozlabs.org; Mon, 29 Oct 2018 11:52:42 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34403) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9Lg-0008Sr-Ec for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:21:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gH9Lb-0003PS-Td for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:21:00 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:39627 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gH9Lb-0003Ja-Dg for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:20:55 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 370081A2254; Mon, 29 Oct 2018 16:20:26 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 048CE1A23F8; Mon, 29 Oct 2018 16:20:26 +0100 (CET) From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Mon, 29 Oct 2018 16:20:17 +0100 Message-Id: <1540826418-5501-27-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL 26/27] linux-user: Determine the desired FPU mode from MIPS.abiflags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Stefan Markovic Floating-point mode is calculated from MIPS.abiflags FP ABI value (based on kernel implementation). Illegal combinations are rejected. Reviewed-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- linux-user/mips/cpu_loop.c | 75 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index c9c20cf..97e4957 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -740,6 +740,34 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) struct image_info *info = ts->info; int i; + struct mode_req { + bool single; + bool soft; + bool fr1; + bool frdefault; + bool fre; + }; + + static const struct mode_req fpu_reqs[] = { + [MIPS_ABI_FP_ANY] = { true, true, true, true, true }, + [MIPS_ABI_FP_DOUBLE] = { false, false, false, true, true }, + [MIPS_ABI_FP_SINGLE] = { true, false, false, false, false }, + [MIPS_ABI_FP_SOFT] = { false, true, false, false, false }, + [MIPS_ABI_FP_OLD_64] = { false, false, false, false, false }, + [MIPS_ABI_FP_XX] = { false, false, true, true, true }, + [MIPS_ABI_FP_64] = { false, false, true, false, false }, + [MIPS_ABI_FP_64A] = { false, false, true, false, true } + }; + + /* + * Mode requirements when .MIPS.abiflags is not present in the ELF. + * Not present means that everything is acceptable except FR1. + */ + static struct mode_req none_req = { true, true, false, true, true }; + + struct mode_req prog_req; + struct mode_req interp_req; + for(i = 0; i < 32; i++) { env->active_tc.gpr[i] = regs->regs[i]; } @@ -747,6 +775,53 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) if (regs->cp0_epc & 1) { env->hflags |= MIPS_HFLAG_M16; } + +#ifdef TARGET_ABI_MIPSO32 +# define MAX_FP_ABI MIPS_ABI_FP_64A +#else +# define MAX_FP_ABI MIPS_ABI_FP_SOFT +#endif + if ((info->fp_abi > MAX_FP_ABI && info->fp_abi != MIPS_ABI_FP_UNKNOWN) + || (info->interp_fp_abi > MAX_FP_ABI && + info->interp_fp_abi != MIPS_ABI_FP_UNKNOWN)) { + fprintf(stderr, "qemu: Unexpected FPU mode\n"); + exit(1); + } + + prog_req = (info->fp_abi == MIPS_ABI_FP_UNKNOWN) ? none_req + : fpu_reqs[info->fp_abi]; + interp_req = (info->interp_fp_abi == MIPS_ABI_FP_UNKNOWN) ? none_req + : fpu_reqs[info->interp_fp_abi]; + + prog_req.single &= interp_req.single; + prog_req.soft &= interp_req.soft; + prog_req.fr1 &= interp_req.fr1; + prog_req.frdefault &= interp_req.frdefault; + prog_req.fre &= interp_req.fre; + + bool cpu_has_mips_r2_r6 = env->insn_flags & ISA_MIPS32R2 || + env->insn_flags & ISA_MIPS64R2 || + env->insn_flags & ISA_MIPS32R6 || + env->insn_flags & ISA_MIPS64R6; + + if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1) { + env->CP0_Config5 |= (1 << CP0C5_FRE); + if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) { + env->hflags |= MIPS_HFLAG_FRE; + } + } else if ((prog_req.fr1 && prog_req.frdefault) || + (prog_req.single && !prog_req.frdefault)) { + if ((env->active_fpu.fcr0 & (1 << FCR0_F64) + && cpu_has_mips_r2_r6) || prog_req.fr1) { + env->CP0_Status |= (1 << CP0St_FR); + env->hflags |= MIPS_HFLAG_F64; + } + } else if (!prog_req.fre && !prog_req.frdefault && + !prog_req.fr1 && !prog_req.single && !prog_req.soft) { + fprintf(stderr, "qemu: Can't find a matching FPU mode\n"); + exit(1); + } + if (env->insn_flags & ISA_NANOMIPS32) { return; } From patchwork Mon Oct 29 15:20:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 990350 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42kK9Z4481z9s3Z for ; Tue, 30 Oct 2018 03:02:10 +1100 (AEDT) Received: from localhost ([::1]:46450 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9zT-0007EA-TI for incoming@patchwork.ozlabs.org; Mon, 29 Oct 2018 12:02:07 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34577) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9Lu-0000GO-VV for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:21:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gH9Lp-0003ZB-Sw for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:21:14 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:40260 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gH9Lo-0003PA-W1 for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:21:09 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 401A31A23CF; Mon, 29 Oct 2018 16:20:26 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 0E5461A2412; Mon, 29 Oct 2018 16:20:26 +0100 (CET) From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Mon, 29 Oct 2018 16:20:18 +0100 Message-Id: <1540826418-5501-28-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1540826418-5501-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL 27/27] linux-user: Add prctl() PR_SET_FP_MODE and PR_GET_FP_MODE implementations X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Stefan Markovic Implement MIPS specific prctl() PR_SET_FP_MODE and PR_GET_FP_MODE emulation. Reviewed-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- linux-user/mips/target_syscall.h | 2 ++ linux-user/mips64/target_syscall.h | 2 ++ linux-user/syscall.c | 62 +++++++++++++++++++++++++++++++++++--- 3 files changed, 62 insertions(+), 4 deletions(-) diff --git a/linux-user/mips/target_syscall.h b/linux-user/mips/target_syscall.h index 33177af..d5509a3 100644 --- a/linux-user/mips/target_syscall.h +++ b/linux-user/mips/target_syscall.h @@ -247,5 +247,7 @@ static inline abi_ulong target_shmlba(CPUMIPSState *env) /* MIPS-specific prctl() options */ #define TARGET_PR_SET_FP_MODE 45 #define TARGET_PR_GET_FP_MODE 46 +#define TARGET_PR_FP_MODE_FR (1 << 0) +#define TARGET_PR_FP_MODE_FRE (1 << 1) #endif /* MIPS_TARGET_SYSCALL_H */ diff --git a/linux-user/mips64/target_syscall.h b/linux-user/mips64/target_syscall.h index c1160e6..8ccc468 100644 --- a/linux-user/mips64/target_syscall.h +++ b/linux-user/mips64/target_syscall.h @@ -244,5 +244,7 @@ static inline abi_ulong target_shmlba(CPUMIPSState *env) /* MIPS-specific prctl() options */ #define TARGET_PR_SET_FP_MODE 45 #define TARGET_PR_GET_FP_MODE 46 +#define TARGET_PR_FP_MODE_FR (1 << 0) +#define TARGET_PR_FP_MODE_FRE (1 << 1) #endif /* MIPS64_TARGET_SYSCALL_H */ diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 15b03e1..810a58b 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -9529,11 +9529,65 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1, #endif #ifdef TARGET_MIPS case TARGET_PR_GET_FP_MODE: - /* TODO: Implement TARGET_PR_SET_FP_MODE handling.*/ - return -TARGET_EINVAL; + { + CPUMIPSState *env = ((CPUMIPSState *)cpu_env); + ret = 0; + if (env->CP0_Status & (1 << CP0St_FR)) { + ret |= TARGET_PR_FP_MODE_FR; + } + if (env->CP0_Config5 & (1 << CP0C5_FRE)) { + ret |= TARGET_PR_FP_MODE_FRE; + } + return ret; + } case TARGET_PR_SET_FP_MODE: - /* TODO: Implement TARGET_PR_GET_FP_MODE handling.*/ - return -TARGET_EINVAL; + { + CPUMIPSState *env = ((CPUMIPSState *)cpu_env); + bool old_fr = env->CP0_Status & (1 << CP0St_FR); + bool new_fr = arg2 & TARGET_PR_FP_MODE_FR; + bool new_fre = arg2 & TARGET_PR_FP_MODE_FRE; + + if (new_fr && !(env->active_fpu.fcr0 & (1 << FCR0_F64))) { + /* FR1 is not supported */ + return -TARGET_EOPNOTSUPP; + } + if (!new_fr && (env->active_fpu.fcr0 & (1 << FCR0_F64)) + && !(env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) { + /* cannot set FR=0 */ + return -TARGET_EOPNOTSUPP; + } + if (new_fre && !(env->active_fpu.fcr0 & (1 << FCR0_FREP))) { + /* Cannot set FRE=1 */ + return -TARGET_EOPNOTSUPP; + } + + int i; + fpr_t *fpr = env->active_fpu.fpr; + for (i = 0; i < 32 ; i += 2) { + if (!old_fr && new_fr) { + fpr[i].w[!FP_ENDIAN_IDX] = fpr[i + 1].w[FP_ENDIAN_IDX]; + } else if (old_fr && !new_fr) { + fpr[i + 1].w[FP_ENDIAN_IDX] = fpr[i].w[!FP_ENDIAN_IDX]; + } + } + + if (new_fr) { + env->CP0_Status |= (1 << CP0St_FR); + env->hflags |= MIPS_HFLAG_F64; + } else { + env->CP0_Status &= ~(1 << CP0St_FR); + } + if (new_fre) { + env->CP0_Config5 |= (1 << CP0C5_FRE); + if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) { + env->hflags |= MIPS_HFLAG_FRE; + } + } else { + env->CP0_Config5 &= ~(1 << CP0C5_FRE); + } + + return 0; + } #endif /* MIPS */ #ifdef TARGET_AARCH64 case TARGET_PR_SVE_SET_VL: