| Message ID | 1534431497-1385-23-git-send-email-aleksandar.markovic@rt-rk.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add nanoMIPS support to QEMU | expand |
On 08/16/2018 07:57 AM, Aleksandar Markovic wrote: > From: Yongbok Kim <yongbok.kim@mips.com> > > Add emulation of nanoMIPS 16-bit branch instructions. > > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> > Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> > Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com> > --- > target/mips/translate.c | 36 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 36 insertions(+) This patch needs the gen_compute_compact_branch_nm you add in patch 39. All of the uses of gen_compute_branch are incorrect. r~
> From: Richard Henderson <richard.henderson@linaro.org> > Sent: Thursday, August 16, 2018 6:33 PM > > Subject: Re: [PATCH v9 22/84] target/mips: Add emulation of nanoMIPS 16-bit branch instructions > > On 08/16/2018 07:57 AM, Aleksandar Markovic wrote: > > From: Yongbok Kim <yongbok.kim@mips.com> > > > > Add emulation of nanoMIPS 16-bit branch instructions. > > > > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > > Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> > > Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> > > Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com> > > --- > > target/mips/translate.c | 36 ++++++++++++++++++++++++++++++++++++ > > 1 file changed, 36 insertions(+) > > This patch needs the gen_compute_compact_branch_nm you add in patch 39. > All of the uses of gen_compute_branch are incorrect. > > > r~ Hi, Richard, The gen_compute_branch() will be eliminated from nanoMIPS code accross the board. This will be included in v10. That change has been worked on in last few days, but didn't make it to be included in v9. Thanks, Aleksandar
diff --git a/target/mips/translate.c b/target/mips/translate.c index f9ec95b..05c8b8f 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -16746,14 +16746,50 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx) case NM_SWGP16: break; case NM_BC16: + gen_compute_branch(ctx, OPC_BEQ, 2, 0, 0, + (sextract32(ctx->opcode, 0, 1) << 10) | + (extract32(ctx->opcode, 1, 9) << 1), 0); break; case NM_BALC16: + gen_compute_branch(ctx, OPC_BGEZAL, 2, 0, 0, + (sextract32(ctx->opcode, 0, 1) << 10) | + (extract32(ctx->opcode, 1, 9) << 1), 0); break; case NM_BEQZC16: + gen_compute_branch(ctx, OPC_BEQ, 2, rt, 0, + (sextract32(ctx->opcode, 0, 1) << 7) | + (extract32(ctx->opcode, 1, 6) << 1), 0); break; case NM_BNEZC16: + gen_compute_branch(ctx, OPC_BNE, 2, rt, 0, + (sextract32(ctx->opcode, 0, 1) << 7) | + (extract32(ctx->opcode, 1, 6) << 1), 0); break; case NM_P16_BR: + switch (ctx->opcode & 0xf) { + case 0: + /* P16.JRC */ + switch (extract32(ctx->opcode, 4, 1)) { + case NM_JRC: + gen_compute_branch(ctx, OPC_JR, 2, + extract32(ctx->opcode, 5, 5), 0, 0, 0); + break; + case NM_JALRC16: + gen_compute_branch(ctx, OPC_JALR, 2, + extract32(ctx->opcode, 5, 5), 31, 0, 0); + break; + } + break; + default: + { + /* P16.BRI */ + uint32_t opc = extract32(ctx->opcode, 4, 3) < + extract32(ctx->opcode, 7, 3) ? OPC_BEQ : OPC_BNE; + gen_compute_branch(ctx, opc, 2, rs, rt, + extract32(ctx->opcode, 0, 4) << 1, 0); + } + break; + } break; case NM_P16_SR: break;