mbox series

[v9,00/84] Add nanoMIPS support to QEMU

Message ID 1534431497-1385-1-git-send-email-aleksandar.markovic@rt-rk.com
Headers show
Series Add nanoMIPS support to QEMU | expand

Message

Aleksandar Markovic Aug. 16, 2018, 2:56 p.m. UTC 
From: Aleksandar Markovic <amarkovic@wavecomp.com>

v8->v9:

  - reoganized (moved/squashed) patches so that clang build bisect
     works (as the result, number of patches dropped from 87 to 84)
  - re-examined and reworked 32-bit nanoMIPS branch instructions
  - minor improvements in commit messages  
  - rebased to the latest code

v7->v8:

  - the series is slightly reorganized so that:
      - patches 1-19 are fixes and improvements that are not
      dependent on the existence of nanoMIPS (even though most
      of them are logicaly connected to (and necessary for)
      nanoMIPS support) - they fix and improve pre-nanoMIPS code
      - patches 20-65 introduce core nanoMIPS functionality, but
      do not contain any dependence on or reference to nanoMIPS
      Linux ABI
      - patches 66-87 mostly deal with Linux user mode-related
      nanoMIPS functionality, therefore dependent on nanoMIPS
      Linux ABI
  - the series will probably be split into three (corresponding
      to the organization mentioned above) in near future

  - added support for availability control via bit config XNP
  - fixed availabitily control for LLWP/SCWP
  - added support for availability control via bit config MT
  - fixed availabitily control for pre-nanoMIPS MT ASE
  - fixed availabitily control for nanoMIPS MT ASE
  - completely removed case-statements defined by integer range
      from translate.c
  - patch on nanoMIPS specifics in ELF headers split into two
  - patch on GT64120-related functionality in nanoMIPS bootloader
      updated with comments and reorganizes with respect to
      endianness
  - replaced one instance of shift/mask with extract32()
  - fixed one instance of missing default case in decoding engine
  - removed several instances of unnecessary default case in
    decoding engine
  - minor tweaks related to variable scope and naming
  - fixed several spelling mistakes in commit messages
  - rebased to the latest code

v6->v7:

  - found a better place for MIPS_ARCH in elf.h
  - improved patch for LLWP and SCWP
  - fixed missing availability control, alignment, usage
    of extract32() in DSP patches
  - added disassembler support for microMIPS and nanoMIPS
  - removed unnecessary addition of one empty line in the
    patch on WR bit
  - improved statx() syscall translation
  - improved nanoMIPS items in binfmt script
  - amended pre-nanoMIPS items in qemu-doc.texi
  - added nanoMIPS items in qemu-doc.texi
  - changed slightly patch order to be logicaly more
    comprehensive 
  - rebased to the latest code
  - NOTE: there will be some sheckpatch.pl errors and warning
    for this series; however, we think those are flase positives
    in these particular circumstances - therefore we will not
    change any patch related to these checkpatch.pl messages

v5->v6:

  - used names offset and imm instead of rd and rs when
    appropriate
  - used gen_op_addr_addi when appropriate in one more place
  - avoided usage of tcg_temp_local_new
  - avoided unnecessary sign extension related to addr_add
  - fixed unprotected storing to cpu_gpr[0]
  - removed some unnecessary testing for ISA_NANOMIPS
  - updated patch for LLWP and SCWP
  - extract32 inserted instead of shift/mask in DSP patches
  - removed useless casts from DSP patches
  - reorganized functions to eliminated duplicated loading of
    gpr values into tcg variables in DSP patches
  - check Config1.WR bit for Watch registers only when using
    in runtime
  - removed duplicated check for bad address in PC register
  - added support for statx system call
  - updated script qemu-binfmt-conf.sh for nanoMIPS
  - rebased to the latest code

v4->v5:

  - merged series "Mips maintenance and misc fixes and improvements"
    and this one for easier handling (there are build dependencies)
  - eliminated shadow variables from translate.c
  - replaced shift/mask combination with extract32()
  - added new function gen_op_addr_addi()
  - added patch for LLWP and SCWP
  - added "fall through" comments at appropriate places
  - eliminated micromips flag from I7200 definition
  - numerous other enhancements originating from reviewer's
    comments
  - some of the patches split into two or more for easier
    handling and review
  - rebased to the latest code

v3->v4:

  - added support for nanoMIPS user mode functionality and
    configuration
  - DSP patch split into three for easier review and handling
  - corrected indentation in all decoding engine patches
  - shift/mask replaced with equivalent extract32() in some
    patches
  - added missing default cases in some patches
  - refactored invocation logic aroung decode_nanomips_opc()
  - improved comments before decode_gpr_XXX() utilities
  - all four decode_gpr_XXX() are now in a single patch
  - two patches on updating BadInstr and related registers
    are now merged, and execution logic improved
  - minor formatting corrections
  - rebased to the latest code

v2->v3:

  - added support for nanoMIPS-specifics in ELF headers
  - added support for CP0 Config0.WR bit
  - updated I7200 definition
  - improved indentation of some switch statements
  - slight reorganization of patches (splitting, order)
  - rebased to the latest code

v1->v2:

  - added DSP ASE support
  - added MT ASE support
  - added GDB XML support
  - order of patches changed
  - commit messages and patch title improved across the board
  - obsolete email addresses for authors and cosigners replaced
    with the right ones
  - some functions renamed to reflect better the documentation
  - some macros renamed to reflect better their nanoMIPS nature
  - streamlined formatting
  - some of other reviewer's comments addressed, but the majority
    was not; this is because the focus of this version was on
    completing the functionality as much as possible; remaining
    comments will be addressed in the subsequent versions of this
    series

This series of patches implements recently announced nanoMIPS on QEMU.
nanoMIPS is a variable length ISA containing 16, 32 and 48-bit wide
instructions. It is designed to be portable at assembly level with
other MIPS and microMIPS code, but contains a number of changes that
enhance code density and efficiency. The largest portion of patches
is nanoMIPS decoding engine.

For more information, please refer to the following link:

https://www.mips.com/products/architectures/nanomips/

Aleksandar Markovic (16):
  MAINTAINERS: Update target/mips maintainer's email addresses
  target/mips: Avoid case statements formulated by ranges - part 1
  target/mips: Mark switch fallthroughs with interpretable comments
  target/mips: Fix two instances of shadow variables
  target/mips: Update some CP0 registers bit definitions
  elf: Remove duplicate preprocessor constant definition
  elf: Add ELF flags for MIPS machine variants
  linux-user: Update MIPS syscall numbers up to kernel 4.18 headers
  qemu-doc: Amend MIPS-related items
  target/mips: Add preprocessor constants for nanoMIPS
  target/mips: Add placeholder and invocation of decode_nanomips_opc()
  target/mips: Add nanoMIPS decoding and extraction utilities
  elf: Relax MIPS' elf_check_arch() to accept EM_NANOMIPS too
  elf: Don't check FCR31_NAN2008 bit for nanoMIPS
  linux-user: Update syscall_defs.h header for nanoMIPS
  qemu-doc: Add nanoMIPS-related items

Aleksandar Rikalo (18):
  target/mips: Avoid case statements formulated by ranges - part 2
  linux-user: Add preprocessor availability control to some syscalls
  target/mips: Implement emulation of nanoMIPS LLWP/SCWP pair
  target/mips: Fix pre-nanoMIPS MT ASE instructions availability control
  elf: Add EM_NANOMIPS value as a valid one for e_machine field
  elf: On elf loading, treat both EM_MIPS and EM_NANOMIPS as legal for
    MIPS
  elf: Add nanoMIPS specific variations in ELF header fields
  linux-user: Add syscall numbers for nanoMIPS
  linux-user: Add target_signal.h header for nanoMIPS
  linux-user: Add termbits.h header for nanoMIPS
  linux-user: Add target_fcntl.h header for nanoMIPS
  linux-user: Add sockbits.h header for nanoMIPS
  linux-user: Add target_syscall.h header for nanoMIPS
  linux-user: Add support for nanoMIPS signal trampoline
  linux-user: Amend support for sigaction() syscall for nanoMIPS
  linux-user: Add support for statx() syscall for all platforms
  linux-user: Add support for nanoMIPS core files
  linux-user: Add nanoMIPS support in scripts/qemu-binfmt-conf.sh

Dimitrije Nikolic (5):
  linux-user: Add target_cpu.h header for nanoMIPS
  linux-user: Add target_structs.h header for nanoMIPS
  linux-user: Add target_elf.h header for nanoMIPS
  linux-user: Add signal.c for nanoMIPS
  linux-user: Add cpu_loop.c for nanoMIPS

James Hogan (5):
  target/mips: Implement emulation of nanoMIPS EXTW instruction
  target/mips: Adjust exception_resume_pc() for nanoMIPS
  target/mips: Adjust set_hflags_for_handler() for nanoMIPS
  target/mips: Adjust set_pc() for nanoMIPS
  gdbstub: Disable handling of nanoMIPS ISA bit in the MIPS gdbstub

Matthew Fortune (4):
  target/mips: Implement emulation of nanoMIPS ROTX instruction
  disas: Add support for microMIPS and nanoMIPS
  target/mips: Add handling of ISA mode bit for nanoMIPS
  mips_malta: Add basic nanoMIPS boot code for Malta board

Paul Burton (1):
  mips_malta: Add setting up GT64120 BARs to the nanoMIPS bootloader

Stefan Markovic (17):
  target/mips: Add CP0 BadInstrX register
  target/mips: Implement CP0 Config1.WR bit functionality
  target/mips: Add nanoMIPS DSP ASE opcodes
  target/mips: Add emulation of nanoMIPS 16-bit save and restore
    instructions
  target/mips: Add emulation of nanoMIPS 32-bit branch instructions
  target/mips: Implement MT ASE support for nanoMIPS
  target/mips: Add emulation of DSP ASE for nanoMIPS - part 1
  target/mips: Add emulation of DSP ASE for nanoMIPS - part 2
  target/mips: Add emulation of DSP ASE for nanoMIPS - part 3
  target/mips: Add emulation of DSP ASE for nanoMIPS - part 4
  target/mips: Add emulation of DSP ASE for nanoMIPS - part 5
  target/mips: Add emulation of DSP ASE for nanoMIPS - part 6
  target/mips: Add updating BadInstr, BadInstrP, BadInstrX for nanoMIPS
  mips_malta: Fix semihosting argument passing for nanoMIPS bare metal
  target/mips: Add definition of nanoMIPS I7200 CPU
  linux-user: Add nanoMIPS linux user mode configuration support
  gdbstub: Add XML support for GDB for nanoMIPS

Yongbok Kim (18):
  target/mips: Don't update BadVAddr register in Debug Mode
  target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0
  target/mips: Add nanoMIPS base instruction set opcodes
  target/mips: Add emulation of nanoMIPS 16-bit arithmetic instructions
  target/mips: Add emulation of nanoMIPS 16-bit branch instructions
  target/mips: Add emulation of nanoMIPS 16-bit shift instructions
  target/mips: Add emulation of nanoMIPS 16-bit misc instructions
  target/mips: Add emulation of nanoMIPS 16-bit load and store
    instructions
  target/mips: Add emulation of nanoMIPS 16-bit logic instructions
  target/mips: Add emulation of some common nanoMIPS 32-bit instructions
  target/mips: Add emulation of nanoMIPS instructions MOVE.P and
    MOVE.PREV
  target/mips: Add emulation of nanoMIPS 48-bit instructions
  target/mips: Add emulation of nanoMIPS FP instructions
  target/mips: Add emulation of misc nanoMIPS instructions (pool32a0)
  target/mips: Add emulation of misc nanoMIPS instructions (pool32axf)
  target/mips: Add emulation of misc nanoMIPS instructions (p_lsx)
  target/mips: Add emulation of nanoMIPS 32-bit load and store
    instructions
  target/mips: Fix ERET/ERETNC behavior related to ADEL exception

 .mailmap                                |     7 +-
 MAINTAINERS                             |    12 +-
 configure                               |    13 +-
 default-configs/nanomips-linux-user.mak |     1 +
 disas/Makefile.objs                     |     1 +
 disas/mips.c                            |   358 +-
 disas/nanomips.cpp                      | 15752 ++++++++++++++++++++++++++++++
 disas/nanomips.h                        |  1208 +++
 gdb-xml/nanomips-cp0.xml                |    13 +
 gdb-xml/nanomips-cpu.xml                |    44 +
 gdb-xml/nanomips-dsp.xml                |    20 +
 gdb-xml/nanomips-fpu.xml                |    45 +
 gdb-xml/nanomips-linux.xml              |    20 +
 hw/mips/mips_malta.c                    |   212 +-
 include/disas/bfd.h                     |     1 +
 include/elf.h                           |    44 +-
 include/hw/elf_ops.h                    |     8 +
 linux-user/elfload.c                    |    12 +-
 linux-user/mips/cpu_loop.c              |    36 +-
 linux-user/mips/signal.c                |    36 +-
 linux-user/mips/syscall_nr.h            |     9 +
 linux-user/mips/termbits.h              |     4 +
 linux-user/mips64/syscall_nr.h          |    18 +
 linux-user/nanomips/cpu_loop.c          |     1 +
 linux-user/nanomips/signal.c            |     1 +
 linux-user/nanomips/sockbits.h          |     1 +
 linux-user/nanomips/syscall_nr.h        |   275 +
 linux-user/nanomips/target_cpu.h        |    21 +
 linux-user/nanomips/target_elf.h        |    14 +
 linux-user/nanomips/target_fcntl.h      |    38 +
 linux-user/nanomips/target_signal.h     |    22 +
 linux-user/nanomips/target_structs.h    |     1 +
 linux-user/nanomips/target_syscall.h    |    30 +
 linux-user/nanomips/termbits.h          |     1 +
 linux-user/strace.c                     |    14 +-
 linux-user/syscall.c                    |   150 +-
 linux-user/syscall_defs.h               |    95 +-
 qemu-doc.texi                           |    15 +-
 scripts/qemu-binfmt-conf.sh             |    16 +-
 target/mips/cpu.c                       |    12 +-
 target/mips/cpu.h                       |   164 +-
 target/mips/gdbstub.c                   |    13 +-
 target/mips/helper.c                    |    35 +-
 target/mips/helper.h                    |     2 +
 target/mips/internal.h                  |     9 +-
 target/mips/machine.c                   |     5 +-
 target/mips/mips-defs.h                 |     4 +
 target/mips/op_helper.c                 |   113 +-
 target/mips/translate.c                 |  5132 +++++++++-
 target/mips/translate_init.inc.c        |    39 +
 50 files changed, 23853 insertions(+), 244 deletions(-)
 create mode 100644 default-configs/nanomips-linux-user.mak
 create mode 100644 disas/nanomips.cpp
 create mode 100644 disas/nanomips.h
 create mode 100644 gdb-xml/nanomips-cp0.xml
 create mode 100644 gdb-xml/nanomips-cpu.xml
 create mode 100644 gdb-xml/nanomips-dsp.xml
 create mode 100644 gdb-xml/nanomips-fpu.xml
 create mode 100644 gdb-xml/nanomips-linux.xml
 create mode 100644 linux-user/nanomips/cpu_loop.c
 create mode 100644 linux-user/nanomips/signal.c
 create mode 100644 linux-user/nanomips/sockbits.h
 create mode 100644 linux-user/nanomips/syscall_nr.h
 create mode 100644 linux-user/nanomips/target_cpu.h
 create mode 100644 linux-user/nanomips/target_elf.h
 create mode 100644 linux-user/nanomips/target_fcntl.h
 create mode 100644 linux-user/nanomips/target_signal.h
 create mode 100644 linux-user/nanomips/target_structs.h
 create mode 100644 linux-user/nanomips/target_syscall.h
 create mode 100644 linux-user/nanomips/termbits.h

Comments

Aleksandar Markovic Aug. 16, 2018, 4:55 p.m. UTC | #1 
> From: Richard Henderson <richard.henderson@linaro.org>
> Sent: Thursday, August 16, 2018 6:31 PM
> 
> Subject: Re: [PATCH v9 39/84] target/mips: Add emulation of nanoMIPS 32-bit branch instructions
> 
> On 08/16/2018 07:57 AM, Aleksandar Markovic wrote:
> > +    } else {
> > +        /* Conditional compact branch */
> > +        TCGLabel *fs = gen_new_label();
> > +        save_cpu_state(ctx, 0);
> 
> I will note that save_cpu_state(ctx, 0) is concerned about updating the BMASK
> bits for branch delay slots, which nanomips does not have.  The function could
> probably usefully be renamed so that's clearer.
> 

This and other similar cases will be fixed in v10. Perhaps even the naming of save_cpu_state().

> 
> >      case NM_P_J:
> > +        switch (extract32(ctx->opcode, 12, 4)) {
> > +        case NM_JALRC:
> > +        case NM_JALRC_HB:
> > +            gen_compute_branch(ctx, OPC_JALR, 4, rs, rt, 0, 0);
> > +            break;
> 
> All of these branches need to be using the new functions that you just added.
> There are even more incorrect uses to follow.
> 

All occurrences will be fixed in v10.
Aleksandar Markovic Aug. 16, 2018, 5:06 p.m. UTC | #2 
> From: Richard Henderson <richard.henderson@linaro.org>
> Sent: Thursday, August 16, 2018 6:37 PM
> 
> Subject: Re: [PATCH v9 40/84] target/mips: Fix pre-nanoMIPS MT ASE instructions availability control
> 
> On 08/16/2018 07:57 AM, Aleksandar Markovic wrote:
> > From: Aleksandar Rikalo <arikalo@wavecomp.com>
> >
> > Use bits from configuration registers for availability control
> > of MT ASE instructions, rather than only ISA_MT bit in insn_flags.
> > This is done by adding a field in hflags for MT bit, and adding
> > functions check_mt() and check_cp0_mt().
> >
> > Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> > Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> > Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
> > ---
> >  target/mips/cpu.h       |  3 ++-
> >  target/mips/internal.h  |  6 +++++-
> >  target/mips/translate.c | 45 +++++++++++++++++++++++++++++++++++++--------
> >  3 files changed, 44 insertions(+), 10 deletions(-)
> 
> What was wrong with using insn_flags?
> 

The problem with using ISA_MT from insn_flags is that it doesn't provide the correct availability control. Even though all instructions from MT ASE are related, they are available under different conditions:

Case 1 - DMT, DVPE, EMT, EVPE:
    
    if IsCoprocessorEnabled(0) then
        if Config3 MT then
            <main fuctionality>
        else
            SignalException(ReservedInstruction)
        endif
    else
        SignalException(CoprocessorUnusable, 0)
    endif

Case 2 - FORK, YIELD:

    if Config3 MT then
        <main fuctionality>
    else
        SignalException(ReservedInstruction)
    endif

Case 3 - MFTR, MTTR:

    if IsCoprocessorEnabled(0) then
        <main fuctionality>
    else
        SignalException(CoprocessorUnusable, 0)
    endif

> I'll note that hflags should be reserved for things that can change at runtime.
>  I thought all of these configuration registers were read-only.
> 
> Anyway, with this plus the XNP patch from earlier, you now only have one
> remaining bit within hflags and then that resource is exhausted.
> 

I think some of the previously-implemented similar cases involving read-only bits were handled the same way, and we just built on that. What would you suggest as a more appropriate solution in such cases (of accessing "preset by hardware" bits)?

Regards,
Aleksandar
Richard Henderson Aug. 16, 2018, 5:22 p.m. UTC | #3 
On 08/16/2018 10:06 AM, Aleksandar Markovic wrote:
> I think some of the previously-implemented similar cases involving read-only bits were handled the same way, and we just built on that. What would you suggest as a more appropriate solution in such cases (of accessing "preset by hardware" bits)?

Well, ctx->insn_flags and ctx->CP0_Config1 are good examples.
These are 100% read-only and fixed at cpu instantiation.

I see that CP0_Config3 has one writable bit for micromips, but
is fully readonly for nanomips.  Therefore XNP and MT need not
be copied to hflags because they will never vary.

I'd suggest copying CP0_Config3 to ctx as with Config1.


r~
Aleksandar Markovic Aug. 17, 2018, 1:48 p.m. UTC | #4 
> > I think some of the previously-implemented similar cases involving read-only bits were handled the same way, and we just built on that. What would you suggest as a more appropriate solution in such cases (of accessing "preset by hardware" bits)?
>
> Well, ctx->insn_flags and ctx->CP0_Config1 are good examples.
> These are 100% read-only and fixed at cpu instantiation.
> 
> I see that CP0_Config3 has one writable bit for micromips, but
> is fully readonly for nanomips.  Therefore XNP and MT need not
> be copied to hflags because they will never vary.
> 
> I'd suggest copying CP0_Config3 to ctx as with Config1.
>
>
> r~

Hi, Richard,

The opinion within the team is that we should leave such changes for follow-up clean-up - clean-up of CP0-related functionalities is scheduled anyway soon.

The reason is that the current implementation (in v9) works fine, and this is very late in our dev cycle to change features with no observed bugs.

All other your concerns will be addressed in v10, which is planned to be sent soon.

Yours,
Aleksandar
no-reply@patchew.org Aug. 17, 2018, 5:45 p.m. UTC | #5 
Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 1534431497-1385-1-git-send-email-aleksandar.markovic@rt-rk.com
Subject: [Qemu-devel] [PATCH v9 00/84] Add nanoMIPS support to QEMU

=== TEST SCRIPT BEGIN ===
#!/bin/bash

BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0

git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram

commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
    echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
    if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
        failed=1
        echo
    fi
    n=$((n+1))
done

exit $failed
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 * [new tag]               patchew/20180817173752.19136-1-marcandre.lureau@redhat.com -> patchew/20180817173752.19136-1-marcandre.lureau@redhat.com
Switched to a new branch 'test'
a1a72634da qemu-doc: Add nanoMIPS-related items
6b0e4a5bed gdbstub: Add XML support for GDB for nanoMIPS
f52a089394 gdbstub: Disable handling of nanoMIPS ISA bit in the MIPS gdbstub
5f142a7f45 linux-user: Add nanoMIPS support in scripts/qemu-binfmt-conf.sh
659d8ae1d2 linux-user: Add nanoMIPS linux user mode configuration support
bc2b17acba linux-user: Add support for nanoMIPS core files
f85e52df38 linux-user: Add support for statx() syscall for all platforms
a83b0978d7 linux-user: Amend support for sigaction() syscall for nanoMIPS
2d70411dd7 linux-user: Add cpu_loop.c for nanoMIPS
db9b944cb1 linux-user: Add support for nanoMIPS signal trampoline
f81b94f27d linux-user: Add signal.c for nanoMIPS
69b33591d8 linux-user: Add target_elf.h header for nanoMIPS
dcefb34f92 linux-user: Add target_structs.h header for nanoMIPS
aa2c053141 linux-user: Add target_cpu.h header for nanoMIPS
97cc893282 linux-user: Add target_syscall.h header for nanoMIPS
53ec0f262a linux-user: Add sockbits.h header for nanoMIPS
bca5609efd linux-user: Add target_fcntl.h header for nanoMIPS
d3ddf176f1 linux-user: Update syscall_defs.h header for nanoMIPS
1e743454c7 linux-user: Add termbits.h header for nanoMIPS
7c22c6c329 linux-user: Add target_signal.h header for nanoMIPS
d01af10006 linux-user: Add syscall numbers for nanoMIPS
b2174ff5a4 elf: Add nanoMIPS specific variations in ELF header fields
2e7015c623 target/mips: Add definition of nanoMIPS I7200 CPU
3f96d01420 mips_malta: Fix semihosting argument passing for nanoMIPS bare metal
0573ead99a mips_malta: Add setting up GT64120 BARs to the nanoMIPS bootloader
e6555b01ef mips_malta: Add basic nanoMIPS boot code for Malta board
c143508151 elf: On elf loading, treat both EM_MIPS and EM_NANOMIPS as legal for MIPS
c3dca3b23f elf: Don't check FCR31_NAN2008 bit for nanoMIPS
eefffbac2e elf: Relax MIPS' elf_check_arch() to accept EM_NANOMIPS too
47b7a54ee6 elf: Add EM_NANOMIPS value as a valid one for e_machine field
273d998114 target/mips: Fix ERET/ERETNC behavior related to ADEL exception
caacbe0eb4 target/mips: Adjust set_pc() for nanoMIPS
7b0ee7a295 target/mips: Adjust set_hflags_for_handler() for nanoMIPS
6863647c24 target/mips: Adjust exception_resume_pc() for nanoMIPS
571dfe937a target/mips: Add updating BadInstr, BadInstrP, BadInstrX for nanoMIPS
2a18c544e3 target/mips: Add handling of ISA mode bit for nanoMIPS
9e3f869adc disas: Add support for microMIPS and nanoMIPS
e8e218964c target/mips: Add emulation of DSP ASE for nanoMIPS - part 6
3e47dc67c3 target/mips: Add emulation of DSP ASE for nanoMIPS - part 5
1de728e9e3 target/mips: Add emulation of DSP ASE for nanoMIPS - part 4
820969ddbe target/mips: Add emulation of DSP ASE for nanoMIPS - part 3
f7dd4bb0ff target/mips: Add emulation of DSP ASE for nanoMIPS - part 2
e83aba8000 target/mips: Add emulation of DSP ASE for nanoMIPS - part 1
ad05be4532 target/mips: Implement MT ASE support for nanoMIPS
9cd68df113 target/mips: Fix pre-nanoMIPS MT ASE instructions availability control
111896a725 target/mips: Add emulation of nanoMIPS 32-bit branch instructions
b7beb2231a target/mips: Implement emulation of nanoMIPS LLWP/SCWP pair
c9f518e478 target/mips: Add emulation of nanoMIPS 32-bit load and store instructions
e9280f3f61 target/mips: Implement emulation of nanoMIPS EXTW instruction
1a2ba0c63f target/mips: Implement emulation of nanoMIPS ROTX instruction
03c8c9b0de target/mips: Add emulation of misc nanoMIPS instructions (p_lsx)
a4b29366b0 target/mips: Add emulation of misc nanoMIPS instructions (pool32axf)
2d5e4a0900 target/mips: Add emulation of misc nanoMIPS instructions (pool32a0)
3047cb0427 target/mips: Add emulation of nanoMIPS FP instructions
325d0832ee target/mips: Add emulation of nanoMIPS 48-bit instructions
90e962edc4 target/mips: Add emulation of nanoMIPS instructions MOVE.P and MOVE.PREV
8bb5f354f0 target/mips: Add emulation of some common nanoMIPS 32-bit instructions
92dd2d2010 target/mips: Add emulation of nanoMIPS 16-bit save and restore instructions
8b250d1857 target/mips: Add emulation of nanoMIPS 16-bit logic instructions
a59cb3b7ce target/mips: Add emulation of nanoMIPS 16-bit load and store instructions
e52f2bed61 target/mips: Add emulation of nanoMIPS 16-bit misc instructions
147f444f9e target/mips: Add emulation of nanoMIPS 16-bit shift instructions
911ac40da5 target/mips: Add emulation of nanoMIPS 16-bit branch instructions
33bebcc220 target/mips: Add emulation of nanoMIPS 16-bit arithmetic instructions
f27c375d46 target/mips: Add nanoMIPS decoding and extraction utilities
5f78b4fe03 target/mips: Add placeholder and invocation of decode_nanomips_opc()
e808b9763d target/mips: Add nanoMIPS DSP ASE opcodes
2ec0c6f5cb target/mips: Add nanoMIPS base instruction set opcodes
92cf9adc27 target/mips: Add preprocessor constants for nanoMIPS
9b2a73f39d qemu-doc: Amend MIPS-related items
e9fb9d27a8 linux-user: Add preprocessor availability control to some syscalls
da5d92d0ad linux-user: Update MIPS syscall numbers up to kernel 4.18 headers
cb9622e05d elf: Add ELF flags for MIPS machine variants
2b7defe4b2 elf: Remove duplicate preprocessor constant definition
7757c99e46 target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0
d0745caa77 target/mips: Don't update BadVAddr register in Debug Mode
caff105e98 target/mips: Implement CP0 Config1.WR bit functionality
89dfd7911a target/mips: Add CP0 BadInstrX register
b27cf9860e target/mips: Update some CP0 registers bit definitions
e00d0228da target/mips: Fix two instances of shadow variables
36f4cc5acb target/mips: Mark switch fallthroughs with interpretable comments
16d2909df0 target/mips: Avoid case statements formulated by ranges - part 2
5a104b9359 target/mips: Avoid case statements formulated by ranges - part 1
649365aaee MAINTAINERS: Update target/mips maintainer's email addresses

=== OUTPUT BEGIN ===
Checking PATCH 1/84: MAINTAINERS: Update target/mips maintainer's email addresses...
Checking PATCH 2/84: target/mips: Avoid case statements formulated by ranges - part 1...
Checking PATCH 3/84: target/mips: Avoid case statements formulated by ranges - part 2...
Checking PATCH 4/84: target/mips: Mark switch fallthroughs with interpretable comments...
Checking PATCH 5/84: target/mips: Fix two instances of shadow variables...
Checking PATCH 6/84: target/mips: Update some CP0 registers bit definitions...
Checking PATCH 7/84: target/mips: Add CP0 BadInstrX register...
Checking PATCH 8/84: target/mips: Implement CP0 Config1.WR bit functionality...
Checking PATCH 9/84: target/mips: Don't update BadVAddr register in Debug Mode...
Checking PATCH 10/84: target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0...
Checking PATCH 11/84: elf: Remove duplicate preprocessor constant definition...
Checking PATCH 12/84: elf: Add ELF flags for MIPS machine variants...
Checking PATCH 13/84: linux-user: Update MIPS syscall numbers up to kernel 4.18 headers...
Checking PATCH 14/84: linux-user: Add preprocessor availability control to some syscalls...
Checking PATCH 15/84: qemu-doc: Amend MIPS-related items...
Checking PATCH 16/84: target/mips: Add preprocessor constants for nanoMIPS...
Checking PATCH 17/84: target/mips: Add nanoMIPS base instruction set opcodes...
Checking PATCH 18/84: target/mips: Add nanoMIPS DSP ASE opcodes...
Checking PATCH 19/84: target/mips: Add placeholder and invocation of decode_nanomips_opc()...
Checking PATCH 20/84: target/mips: Add nanoMIPS decoding and extraction utilities...
Checking PATCH 21/84: target/mips: Add emulation of nanoMIPS 16-bit arithmetic instructions...
Checking PATCH 22/84: target/mips: Add emulation of nanoMIPS 16-bit branch instructions...
Checking PATCH 23/84: target/mips: Add emulation of nanoMIPS 16-bit shift instructions...
Checking PATCH 24/84: target/mips: Add emulation of nanoMIPS 16-bit misc instructions...
Checking PATCH 25/84: target/mips: Add emulation of nanoMIPS 16-bit load and store instructions...
Checking PATCH 26/84: target/mips: Add emulation of nanoMIPS 16-bit logic instructions...
Checking PATCH 27/84: target/mips: Add emulation of nanoMIPS 16-bit save and restore instructions...
Checking PATCH 28/84: target/mips: Add emulation of some common nanoMIPS 32-bit instructions...
Checking PATCH 29/84: target/mips: Add emulation of nanoMIPS instructions MOVE.P and MOVE.PREV...
Checking PATCH 30/84: target/mips: Add emulation of nanoMIPS 48-bit instructions...
Checking PATCH 31/84: target/mips: Add emulation of nanoMIPS FP instructions...
Checking PATCH 32/84: target/mips: Add emulation of misc nanoMIPS instructions (pool32a0)...
Checking PATCH 33/84: target/mips: Add emulation of misc nanoMIPS instructions (pool32axf)...
Checking PATCH 34/84: target/mips: Add emulation of misc nanoMIPS instructions (p_lsx)...
Checking PATCH 35/84: target/mips: Implement emulation of nanoMIPS ROTX instruction...
Checking PATCH 36/84: target/mips: Implement emulation of nanoMIPS EXTW instruction...
Checking PATCH 37/84: target/mips: Add emulation of nanoMIPS 32-bit load and store instructions...
Checking PATCH 38/84: target/mips: Implement emulation of nanoMIPS LLWP/SCWP pair...
Checking PATCH 39/84: target/mips: Add emulation of nanoMIPS 32-bit branch instructions...
Checking PATCH 40/84: target/mips: Fix pre-nanoMIPS MT ASE instructions availability control...
Checking PATCH 41/84: target/mips: Implement MT ASE support for nanoMIPS...
Checking PATCH 42/84: target/mips: Add emulation of DSP ASE for nanoMIPS - part 1...
Checking PATCH 43/84: target/mips: Add emulation of DSP ASE for nanoMIPS - part 2...
Checking PATCH 44/84: target/mips: Add emulation of DSP ASE for nanoMIPS - part 3...
Checking PATCH 45/84: target/mips: Add emulation of DSP ASE for nanoMIPS - part 4...
Checking PATCH 46/84: target/mips: Add emulation of DSP ASE for nanoMIPS - part 5...
Checking PATCH 47/84: target/mips: Add emulation of DSP ASE for nanoMIPS - part 6...
Checking PATCH 48/84: disas: Add support for microMIPS and nanoMIPS...
ERROR: externs should be avoided in .c files
#330: FILE: disas/mips.c:6074:
+int nanomips_dis(char *buf, unsigned address, unsigned short one,

WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#414: 
new file mode 100644

ERROR: space required before that '*' (ctx:OxV)
#860: FILE: disas/nanomips.cpp:442:
+                if ((cond == 0) || (this->*cond)(op_code)) {
                                           ^

ERROR: space required before that '*' (ctx:OxV)
#888: FILE: disas/nanomips.cpp:470:
+                            dis = (this->*dis_fn)(op_code);
                                          ^

ERROR: space prohibited between function name and open parenthesis '('
#17393: FILE: include/disas/bfd.h:390:
+int print_insn_micromips        (bfd_vma, disassemble_info*);

total: 4 errors, 1 warnings, 17374 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 49/84: target/mips: Add handling of ISA mode bit for nanoMIPS...
Checking PATCH 50/84: target/mips: Add updating BadInstr, BadInstrP, BadInstrX for nanoMIPS...
Checking PATCH 51/84: target/mips: Adjust exception_resume_pc() for nanoMIPS...
Checking PATCH 52/84: target/mips: Adjust set_hflags_for_handler() for nanoMIPS...
Checking PATCH 53/84: target/mips: Adjust set_pc() for nanoMIPS...
Checking PATCH 54/84: target/mips: Fix ERET/ERETNC behavior related to ADEL exception...
Checking PATCH 55/84: elf: Add EM_NANOMIPS value as a valid one for e_machine field...
Checking PATCH 56/84: elf: Relax MIPS' elf_check_arch() to accept EM_NANOMIPS too...
Checking PATCH 57/84: elf: Don't check FCR31_NAN2008 bit for nanoMIPS...
Checking PATCH 58/84: elf: On elf loading, treat both EM_MIPS and EM_NANOMIPS as legal for MIPS...
Checking PATCH 59/84: mips_malta: Add basic nanoMIPS boot code for Malta board...
Checking PATCH 60/84: mips_malta: Add setting up GT64120 BARs to the nanoMIPS bootloader...
Checking PATCH 61/84: mips_malta: Fix semihosting argument passing for nanoMIPS bare metal...
Checking PATCH 62/84: target/mips: Add definition of nanoMIPS I7200 CPU...
Checking PATCH 63/84: elf: Add nanoMIPS specific variations in ELF header fields...
Checking PATCH 64/84: linux-user: Add syscall numbers for nanoMIPS...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#16: 
new file mode 100644

total: 0 errors, 1 warnings, 275 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 65/84: linux-user: Add target_signal.h header for nanoMIPS...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#16: 
new file mode 100644

total: 0 errors, 1 warnings, 22 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 66/84: linux-user: Add termbits.h header for nanoMIPS...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#30: 
new file mode 100644

total: 0 errors, 1 warnings, 11 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 67/84: linux-user: Update syscall_defs.h header for nanoMIPS...
Checking PATCH 68/84: linux-user: Add target_fcntl.h header for nanoMIPS...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#14: 
new file mode 100644

total: 0 errors, 1 warnings, 38 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 69/84: linux-user: Add sockbits.h header for nanoMIPS...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#14: 
new file mode 100644

total: 0 errors, 1 warnings, 1 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 70/84: linux-user: Add target_syscall.h header for nanoMIPS...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#14: 
new file mode 100644

total: 0 errors, 1 warnings, 30 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 71/84: linux-user: Add target_cpu.h header for nanoMIPS...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#14: 
new file mode 100644

total: 0 errors, 1 warnings, 21 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 72/84: linux-user: Add target_structs.h header for nanoMIPS...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#15: 
new file mode 100644

total: 0 errors, 1 warnings, 1 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 73/84: linux-user: Add target_elf.h header for nanoMIPS...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#15: 
new file mode 100644

total: 0 errors, 1 warnings, 14 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 74/84: linux-user: Add signal.c for nanoMIPS...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#113: 
new file mode 100644

total: 0 errors, 1 warnings, 84 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 75/84: linux-user: Add support for nanoMIPS signal trampoline...
Checking PATCH 76/84: linux-user: Add cpu_loop.c for nanoMIPS...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54: 
new file mode 100644

total: 0 errors, 1 warnings, 33 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 77/84: linux-user: Amend support for sigaction() syscall for nanoMIPS...
Checking PATCH 78/84: linux-user: Add support for statx() syscall for all platforms...
WARNING: architecture specific defines should be avoided
#45: FILE: linux-user/syscall.c:10040:
+#if defined(__NR_statx)

total: 0 errors, 1 warnings, 175 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 79/84: linux-user: Add support for nanoMIPS core files...
Checking PATCH 80/84: linux-user: Add nanoMIPS linux user mode configuration support...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#60: 
new file mode 100644

total: 0 errors, 1 warnings, 38 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 81/84: linux-user: Add nanoMIPS support in scripts/qemu-binfmt-conf.sh...
WARNING: line over 80 characters
#30: FILE: scripts/qemu-binfmt-conf.sh:79:
+nanomips_magic='\x7fELF\x01\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\xf9\x00'

ERROR: line over 90 characters
#31: FILE: scripts/qemu-binfmt-conf.sh:80:
+nanomips_mask='\xff\xff\xff\xff\xff\xff\xff\x00\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff'

WARNING: line over 80 characters
#34: FILE: scripts/qemu-binfmt-conf.sh:83:
+nanomipseb_magic='\x7fELF\x01\x02\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\xf9'

ERROR: line over 90 characters
#35: FILE: scripts/qemu-binfmt-conf.sh:84:
+nanomipseb_mask='\xff\xff\xff\xff\xff\xff\xff\x00\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff'

total: 2 errors, 2 warnings, 34 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 82/84: gdbstub: Disable handling of nanoMIPS ISA bit in the MIPS gdbstub...
Checking PATCH 83/84: gdbstub: Add XML support for GDB for nanoMIPS...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34: 
new file mode 100644

total: 0 errors, 1 warnings, 157 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 84/84: qemu-doc: Add nanoMIPS-related items...
=== OUTPUT END ===

Test command exited with code: 1


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Please send your feedback to patchew-devel@redhat.com
Aleksandar Markovic Aug. 21, 2018, 12:33 p.m. UTC | #6 
> > I think some of the previously-implemented similar cases involving read-only bits were handled the same way, and we just built on that. What would you suggest as a more appropriate solution in such cases (of accessing "preset by hardware" bits)?
>
> Well, ctx->insn_flags and ctx->CP0_Config1 are good examples.
> These are 100% read-only and fixed at cpu instantiation.
>
> I see that CP0_Config3 has one writable bit for micromips, but
> is fully readonly for nanomips.  Therefore XNP and MT need not
> be copied to hflags because they will never vary.
>
> I'd suggest copying CP0_Config3 to ctx as with Config1.
>
>
> r~

Hi, Richard,

We ended up implementing this feature the way you suggested in the v11. Sorry about snafu.

Regards,
Aleksandar