Show patches with: Series = [PULL,v2,01/19] hw/riscv: sifive_u: Allow passing custom DTB       |    State = Action Required       |    Archived = No       |   19 patches
Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[PULL,v2,19/19] target/riscv/csr.c : add space before the open parenthesis '(' [PULL,v2,01/19] hw/riscv: sifive_u: Allow passing custom DTB - - 2 - --- 2020-11-03 Alistair Francis New
[PULL,v2,18/19] hw/riscv: microchip_pfsoc: Hook the I2C1 controller [PULL,v2,01/19] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-11-03 Alistair Francis New
[PULL,v2,17/19] hw/riscv: microchip_pfsoc: Correct DDR memory map [PULL,v2,01/19] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-11-03 Alistair Francis New
[PULL,v2,16/19] hw/riscv: microchip_pfsoc: Map the reserved memory at address 0 [PULL,v2,01/19] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-11-03 Alistair Francis New
[PULL,v2,15/19] hw/riscv: microchip_pfsoc: Connect the SYSREG module [PULL,v2,01/19] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-11-03 Alistair Francis New
[PULL,v2,14/19] hw/misc: Add Microchip PolarFire SoC SYSREG module support [PULL,v2,01/19] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-11-03 Alistair Francis New
[PULL,v2,13/19] hw/riscv: microchip_pfsoc: Connect the IOSCB module [PULL,v2,01/19] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-11-03 Alistair Francis New
[PULL,v2,12/19] hw/misc: Add Microchip PolarFire SoC IOSCB module support [PULL,v2,01/19] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-11-03 Alistair Francis New
[PULL,v2,11/19] hw/riscv: microchip_pfsoc: Connect DDR memory controller modules [PULL,v2,01/19] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-11-03 Alistair Francis New
[PULL,v2,10/19] hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support [PULL,v2,01/19] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-11-03 Alistair Francis New
[PULL,v2,09/19] hw/riscv: microchip_pfsoc: Document where to look at the SoC memory maps [PULL,v2,01/19] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-11-03 Alistair Francis New
[PULL,v2,08/19] target/riscv: Add sifive_plic vmstate [PULL,v2,01/19] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-11-03 Alistair Francis New
[PULL,v2,07/19] target/riscv: Add V extension state description [PULL,v2,01/19] hw/riscv: sifive_u: Allow passing custom DTB - - 2 - --- 2020-11-03 Alistair Francis New
[PULL,v2,06/19] target/riscv: Add H extension state description [PULL,v2,01/19] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-11-03 Alistair Francis New
[PULL,v2,05/19] target/riscv: Add PMP state description [PULL,v2,01/19] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-11-03 Alistair Francis New
[PULL,v2,04/19] target/riscv: Add basic vmstate description of CPU [PULL,v2,01/19] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-11-03 Alistair Francis New
[PULL,v2,03/19] target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit [PULL,v2,01/19] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-11-03 Alistair Francis New
[PULL,v2,02/19] hw/riscv: virt: Allow passing custom DTB [PULL,v2,01/19] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-11-03 Alistair Francis New
[PULL,v2,01/19] hw/riscv: sifive_u: Allow passing custom DTB [PULL,v2,01/19] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-11-03 Alistair Francis New