Show patches with: Series = [PULL,01/29] SiFive RISC-V GPIO Device       |    State = Action Required       |    Archived = No       |   29 patches
Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[PULL,29/29] target/riscv: Only flush TLB if SATP.ASID changes [PULL,01/29] SiFive RISC-V GPIO Device - - 1 - --- 2019-05-26 Palmer Dabbelt New
[PULL,28/29] target/riscv: More accurate handling of `sip` CSR [PULL,01/29] SiFive RISC-V GPIO Device - - 1 - --- 2019-05-26 Palmer Dabbelt New
[PULL,27/29] target/riscv: Add checks for several RVC reserved operands [PULL,01/29] SiFive RISC-V GPIO Device - - 1 - --- 2019-05-26 Palmer Dabbelt New
[PULL,26/29] target/riscv: Add the HGATP register masks [PULL,01/29] SiFive RISC-V GPIO Device - - 1 - --- 2019-05-26 Palmer Dabbelt New
[PULL,25/29] target/riscv: Add the HSTATUS register masks [PULL,01/29] SiFive RISC-V GPIO Device - - - - --- 2019-05-26 Palmer Dabbelt New
[PULL,24/29] target/riscv: Add Hypervisor CSR macros [PULL,01/29] SiFive RISC-V GPIO Device - - 1 - --- 2019-05-26 Palmer Dabbelt New
[PULL,23/29] target/riscv: Allow setting mstatus virtulisation bits [PULL,01/29] SiFive RISC-V GPIO Device - - - - --- 2019-05-26 Palmer Dabbelt New
[PULL,22/29] target/riscv: Add the MPV and MTL mstatus bits [PULL,01/29] SiFive RISC-V GPIO Device - - 1 - --- 2019-05-26 Palmer Dabbelt New
[PULL,21/29] target/riscv: Improve the scause logic [PULL,01/29] SiFive RISC-V GPIO Device - - 1 - --- 2019-05-26 Palmer Dabbelt New
[PULL,20/29] target/riscv: Trigger interrupt on MIP update asynchronously [PULL,01/29] SiFive RISC-V GPIO Device - - 1 - --- 2019-05-26 Palmer Dabbelt New
[PULL,19/29] target/riscv: Mark privilege level 2 as reserved [PULL,01/29] SiFive RISC-V GPIO Device - - 1 - --- 2019-05-26 Palmer Dabbelt New
[PULL,18/29] riscv: spike: Add a generic spike machine [PULL,01/29] SiFive RISC-V GPIO Device 1 - 1 - --- 2019-05-26 Palmer Dabbelt New
[PULL,17/29] target/riscv: Deprecate the generic no MMU CPUs [PULL,01/29] SiFive RISC-V GPIO Device - - 1 - --- 2019-05-26 Palmer Dabbelt New
[PULL,16/29] target/riscv: Add a base 32 and 64 bit CPU [PULL,01/29] SiFive RISC-V GPIO Device - - 1 - --- 2019-05-26 Palmer Dabbelt New
[PULL,15/29] target/riscv: Create settable CPU properties [PULL,01/29] SiFive RISC-V GPIO Device - - 1 - --- 2019-05-26 Palmer Dabbelt New
[PULL,14/29] riscv: virt: Allow specifying a CPU via commandline [PULL,01/29] SiFive RISC-V GPIO Device - - 1 - --- 2019-05-26 Palmer Dabbelt New
[PULL,13/29] linux-user/riscv: Add the CPU type as a comment [PULL,01/29] SiFive RISC-V GPIO Device - - - - --- 2019-05-26 Palmer Dabbelt New
[PULL,12/29] target/riscv: Remove unused include of riscv_htif.h for virt board riscv [PULL,01/29] SiFive RISC-V GPIO Device - - 2 - --- 2019-05-26 Palmer Dabbelt New
[PULL,11/29] target/riscv: Remove spaces from register names [PULL,01/29] SiFive RISC-V GPIO Device - - 1 - --- 2019-05-26 Palmer Dabbelt New
[PULL,10/29] target/riscv: Split gen_arith_imm into functional and temp [PULL,01/29] SiFive RISC-V GPIO Device - - 1 - --- 2019-05-26 Palmer Dabbelt New
[PULL,09/29] target/riscv: Split RVC32 and RVC64 insns into separate files [PULL,01/29] SiFive RISC-V GPIO Device - - 1 - --- 2019-05-26 Palmer Dabbelt New
[PULL,08/29] target/riscv: Use pattern groups in insn16.decode [PULL,01/29] SiFive RISC-V GPIO Device - - 1 - --- 2019-05-26 Palmer Dabbelt New
[PULL,07/29] target/riscv: Merge argument decode for RVC shifti [PULL,01/29] SiFive RISC-V GPIO Device - - 1 - --- 2019-05-26 Palmer Dabbelt New
[PULL,06/29] target/riscv: Merge argument sets for insn32 and insn16 [PULL,01/29] SiFive RISC-V GPIO Device - - 1 - --- 2019-05-26 Palmer Dabbelt New
[PULL,05/29] target/riscv: Use --static-decode for decodetree [PULL,01/29] SiFive RISC-V GPIO Device - - 1 - --- 2019-05-26 Palmer Dabbelt New
[PULL,04/29] target/riscv: Name the argument sets for all of insn32 formats [PULL,01/29] SiFive RISC-V GPIO Device - - 1 - --- 2019-05-26 Palmer Dabbelt New
[PULL,03/29] RISC-V: fix single stepping over ret and other branching instructions [PULL,01/29] SiFive RISC-V GPIO Device - - 2 - --- 2019-05-26 Palmer Dabbelt New
[PULL,02/29] target/riscv: Do not allow sfence.vma from user mode [PULL,01/29] SiFive RISC-V GPIO Device - - 2 - --- 2019-05-26 Palmer Dabbelt New
[PULL,01/29] SiFive RISC-V GPIO Device [PULL,01/29] SiFive RISC-V GPIO Device - - 1 - --- 2019-05-26 Palmer Dabbelt New