Show patches with: Series = [v3,01/60] target/riscv: add vector extension field in CPURISCVState       |    State = Action Required       |    Archived = No       |   16 patches
Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[v3,18/60] target/riscv: vector integer divide instructions [v3,01/60] target/riscv: add vector extension field in CPURISCVState - - - - --- 2020-03-09 LIU Zhiwei New
[v3,10/60] target/riscv: vector widening integer add and subtract [v3,01/60] target/riscv: add vector extension field in CPURISCVState - - - - --- 2020-03-09 LIU Zhiwei New
[v3,07/60] target/riscv: add fault-only-first unit stride load [v3,01/60] target/riscv: add vector extension field in CPURISCVState - - - - --- 2020-03-09 LIU Zhiwei New
[v3,04/60] target/riscv: add vector configure instruction [v3,01/60] target/riscv: add vector extension field in CPURISCVState - - - - --- 2020-03-09 LIU Zhiwei New
[v3,03/60] target/riscv: support vector extension csr [v3,01/60] target/riscv: add vector extension field in CPURISCVState - - - - --- 2020-03-09 LIU Zhiwei New
[v3,02/60] target/riscv: implementation-defined constant parameters [v3,01/60] target/riscv: add vector extension field in CPURISCVState - - 2 - --- 2020-03-09 LIU Zhiwei New
[v3,01/60] target/riscv: add vector extension field in CPURISCVState [v3,01/60] target/riscv: add vector extension field in CPURISCVState 1 - 1 - --- 2020-03-09 LIU Zhiwei New
[v3,43/60] target/riscv: narrowing floating-point/integer type-convert instructions [v3,01/60] target/riscv: add vector extension field in CPURISCVState - - - - --- 2020-03-09 LIU Zhiwei New
[v3,50/60] target/riscv: vmfirst find-first-set mask bit [v3,01/60] target/riscv: add vector extension field in CPURISCVState - - - - --- 2020-03-09 LIU Zhiwei New
[v3,49/60] target/riscv: vector mask population count vmpopc [v3,01/60] target/riscv: add vector extension field in CPURISCVState - - - - --- 2020-03-09 LIU Zhiwei New
[v3,48/60] target/riscv: vector mask-register logical instructions [v3,01/60] target/riscv: add vector extension field in CPURISCVState - - - - --- 2020-03-09 LIU Zhiwei New
[v3,47/60] target/riscv: vector widening floating-point reduction instructions [v3,01/60] target/riscv: add vector extension field in CPURISCVState - - - - --- 2020-03-09 LIU Zhiwei New
[v3,46/60] target/riscv: vector single-width floating-point reduction instructions [v3,01/60] target/riscv: add vector extension field in CPURISCVState - - - - --- 2020-03-09 LIU Zhiwei New
[v3,45/60] target/riscv: vector wideing integer reduction instructions [v3,01/60] target/riscv: add vector extension field in CPURISCVState - - - - --- 2020-03-09 LIU Zhiwei New
[v3,44/60] target/riscv: vector single-width integer reduction instructions [v3,01/60] target/riscv: add vector extension field in CPURISCVState - - - - --- 2020-03-09 LIU Zhiwei New
[v3,16/60] target/riscv: vector integer min/max instructions [v3,01/60] target/riscv: add vector extension field in CPURISCVState - - - - --- 2020-03-09 LIU Zhiwei New