mbox series

[v1,0/5] Connect a PCIe host and graphics support to RISC-V

Message ID cover.1529695276.git.alistair.francis@wdc.com
Headers show
Series Connect a PCIe host and graphics support to RISC-V | expand

Message

Alistair Francis June 22, 2018, 7:28 p.m. UTC 
Alistair Francis (5):
  hw/riscv/virtio: Set the soc device tree node as a simple-bus
  hw/riscv/virt: Increase the number of interrupts
  hw/riscv/virt: Connect the Xilinx PCIe
  hw/riscv/virt: Connect a VGA PCIe device
  riscv64-softmmu.mak: Build Virtio Block support

 default-configs/riscv32-softmmu.mak |  6 +++
 default-configs/riscv64-softmmu.mak |  8 ++++
 hw/riscv/virt.c                     | 73 ++++++++++++++++++++++++++++-
 include/hw/riscv/virt.h             |  6 ++-
 4 files changed, 90 insertions(+), 3 deletions(-)

Comments

Palmer Dabbelt Aug. 2, 2018, 5:44 p.m. UTC | #1 
On Fri, 22 Jun 2018 12:28:14 PDT (-0700), alistair.francis@wdc.com wrote:
> Alistair Francis (5):
>   hw/riscv/virtio: Set the soc device tree node as a simple-bus
>   hw/riscv/virt: Increase the number of interrupts
>   hw/riscv/virt: Connect the Xilinx PCIe
>   hw/riscv/virt: Connect a VGA PCIe device
>   riscv64-softmmu.mak: Build Virtio Block support
>
>  default-configs/riscv32-softmmu.mak |  6 +++
>  default-configs/riscv64-softmmu.mak |  8 ++++
>  hw/riscv/virt.c                     | 73 ++++++++++++++++++++++++++++-
>  include/hw/riscv/virt.h             |  6 ++-
>  4 files changed, 90 insertions(+), 3 deletions(-)

Sorry I'm so slow here, I'm still chewing through my patch backlog.  It looks 
like this hasn't made it upstream yet.  I rebased it on top of master but have 
yet to figure out how to make it work, though I think that's on the Linux side.

I haven't yet looked at the code, but I like the functionality so I don't want 
to lose this.  Can you submit a v2 that applies cleanly to master, or do you 
want me to deal with it?
Alistair Francis Aug. 2, 2018, 7:18 p.m. UTC | #2 
Hey,

Sorry for the top post. I’m on holidays at the moment and will be back next week.

I have sent a V2 to the list, I don’t think I CCed you as I know your busy. Once the 3.1 merge window opens I’ll send a new version with all the comments I have received.

Alistair

From: Palmer Dabbelt
Sent: Thursday, 2 August 2018 10:44 AM
To: alistair.francis@wdc.com
Cc: qemu-devel@nongnu.org; alistair.francis@wdc.com; alistair23@gmail.com; Michael Clark
Subject: Re: [PATCH v1 0/5] Connect a PCIe host and graphics support toRISC-V

On Fri, 22 Jun 2018 12:28:14 PDT (-0700), alistair.francis@wdc.com wrote:
> Alistair Francis (5):
>   hw/riscv/virtio: Set the soc device tree node as a simple-bus
>   hw/riscv/virt: Increase the number of interrupts
>   hw/riscv/virt: Connect the Xilinx PCIe
>   hw/riscv/virt: Connect a VGA PCIe device
>   riscv64-softmmu.mak: Build Virtio Block support
>
>  default-configs/riscv32-softmmu.mak |  6 +++
>  default-configs/riscv64-softmmu.mak |  8 ++++
>  hw/riscv/virt.c                     | 73 ++++++++++++++++++++++++++++-
>  include/hw/riscv/virt.h             |  6 ++-
>  4 files changed, 90 insertions(+), 3 deletions(-)

Sorry I'm so slow here, I'm still chewing through my patch backlog.  It looks 
like this hasn't made it upstream yet.  I rebased it on top of master but have 
yet to figure out how to make it work, though I think that's on the Linux side.

I haven't yet looked at the code, but I like the functionality so I don't want 
to lose this.  Can you submit a v2 that applies cleanly to master, or do you 
want me to deal with it?