diff mbox series

[net,V2,07/11] net/mlx5: Verify Hardware supports requested ptp function on a given pin

Message ID 20200728195935.155604-8-saeedm@mellanox.com
State Accepted
Delegated to: David Miller
Headers show
Series [net,V2,01/11] net/mlx5: E-switch, Destroy TSAR when fail to enable the mode | expand

Commit Message

Saeed Mahameed July 28, 2020, 7:59 p.m. UTC 
From: Eran Ben Elisha <eranbe@mellanox.com>

Fix a bug where driver did not verify Hardware pin capabilities for
PTP functions.

Fixes: ee7f12205abc ("net/mlx5e: Implement 1PPS support")
Signed-off-by: Eran Ben Elisha <eranbe@mellanox.com>
Reviewed-by: Ariel Levkovich <lariel@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
---
 .../ethernet/mellanox/mlx5/core/lib/clock.c   | 23 ++++++++++++++++++-
 1 file changed, 22 insertions(+), 1 deletion(-)

Comments

Jakub Kicinski July 28, 2020, 8:20 p.m. UTC | #1 
On Tue, 28 Jul 2020 12:59:31 -0700 Saeed Mahameed wrote:
>  static int mlx5_ptp_verify(struct ptp_clock_info *ptp, unsigned int pin,
>  			   enum ptp_pin_function func, unsigned int chan)
>  {
> -	return (func == PTP_PF_PHYSYNC) ? -EOPNOTSUPP : 0;
> +	struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock,
> +						ptp_info);
> +
> +	switch (func) {
> +	case PTP_PF_NONE:
> +		return 0;
> +	case PTP_PF_EXTTS:
> +		return !(clock->pps_info.pin_caps[pin] &
> +			 MLX5_MTPPS_REG_CAP_PIN_X_MODE_SUPPORT_PPS_IN);
> +	case PTP_PF_PEROUT:
> +		return !(clock->pps_info.pin_caps[pin] &
> +			 MLX5_MTPPS_REG_CAP_PIN_X_MODE_SUPPORT_PPS_OUT);
> +	default:
> +		return -EOPNOTSUPP;
> +	}
> +
> +	return -EOPNOTSUPP;

nit: entirely unnecessary return statement
diff mbox series

Patch

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c
index c6967e1a560b7..284806e331bd8 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c
@@ -408,10 +408,31 @@  static int mlx5_ptp_enable(struct ptp_clock_info *ptp,
 	return 0;
 }
 
+enum {
+	MLX5_MTPPS_REG_CAP_PIN_X_MODE_SUPPORT_PPS_IN = BIT(0),
+	MLX5_MTPPS_REG_CAP_PIN_X_MODE_SUPPORT_PPS_OUT = BIT(1),
+};
+
 static int mlx5_ptp_verify(struct ptp_clock_info *ptp, unsigned int pin,
 			   enum ptp_pin_function func, unsigned int chan)
 {
-	return (func == PTP_PF_PHYSYNC) ? -EOPNOTSUPP : 0;
+	struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock,
+						ptp_info);
+
+	switch (func) {
+	case PTP_PF_NONE:
+		return 0;
+	case PTP_PF_EXTTS:
+		return !(clock->pps_info.pin_caps[pin] &
+			 MLX5_MTPPS_REG_CAP_PIN_X_MODE_SUPPORT_PPS_IN);
+	case PTP_PF_PEROUT:
+		return !(clock->pps_info.pin_caps[pin] &
+			 MLX5_MTPPS_REG_CAP_PIN_X_MODE_SUPPORT_PPS_OUT);
+	default:
+		return -EOPNOTSUPP;
+	}
+
+	return -EOPNOTSUPP;
 }
 
 static const struct ptp_clock_info mlx5_ptp_clock_info = {