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[Committed] RISC-V: Fix --enable-checking=rtl ICE on rv32gc bootstrap

Message ID e2154eb3-1f73-986b-c110-da910959ddab@rivosinc.com
State New
Headers show
Series [Committed] RISC-V: Fix --enable-checking=rtl ICE on rv32gc bootstrap | expand

Commit Message

Patrick O'Neill Sept. 19, 2023, 9:21 p.m. UTC 
Committed, thanks!

The pre-commit hook didn't like the Authored-by format so I changed it
into:
2023-09-19 Juzhe Zhong <juzhe.zhong@rivai.ai>

Patrick


 From 0b9c51dc2fb58911b91889895d00437673d9f4cf Mon Sep 17 00:00:00 2001
From: Patrick O'Neill <patrick@rivosinc.com>
Date: Tue, 19 Sep 2023 10:03:35 -0700
Subject: [PATCH] RISC-V: Fix --enable-checking=rtl ICE on rv32gc bootstrap

Resolves PR 111461.

during RTL pass: expand
offtime.c: In function '__offtime':
offtime.c:79:6: internal compiler error: RTL check: expected elt 0 type 
'e' or 'u', have 'w' (rtx const_int) in riscv_legitimize_const_move, at 
config/riscv/riscv.cc:2176
    79 |   ip = __mon_yday[__isleap(y)];

Tested on rv32gc glibc with --enable-checking=rtl.

2023-09-19 Juzhe Zhong <juzhe.zhong@rivai.ai>

gcc/ChangeLog:

     * config/riscv/riscv.cc (riscv_legitimize_const_move): Eliminate
     src_op_0 var to avoid rtl check error.

Tested-by: Patrick O'Neill <patrick@rivosinc.com>
---
  gcc/config/riscv/riscv.cc | 10 ++++------
  1 file changed, 4 insertions(+), 6 deletions(-)

        emit_insn (gen_rtx_SET (dest, gen_rtx_PLUS (mode, dest, dest_tmp)));
        return;
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Patch

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 8c766e2e2be..9a1e643a6a8 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -2173,16 +2173,14 @@  riscv_legitimize_const_move (machine_mode mode, 
rtx dest, rtx src)
       (const_poly_int:DI [16, 16]) // <- op_1
       ))
     */
-  rtx src_op_0 = XEXP (src, 0);
-
-  if (GET_CODE (src) == CONST && GET_CODE (src_op_0) == PLUS
-    && CONST_POLY_INT_P (XEXP (src_op_0, 1)))
+  if (GET_CODE (src) == CONST && GET_CODE (XEXP (src, 0)) == PLUS
+      && CONST_POLY_INT_P (XEXP (XEXP (src, 0), 1)))
      {
        rtx dest_tmp = gen_reg_rtx (mode);
        rtx tmp = gen_reg_rtx (mode);

-      riscv_emit_move (dest, XEXP (src_op_0, 0));
-      riscv_legitimize_poly_move (mode, dest_tmp, tmp, XEXP (src_op_0, 1));
+      riscv_emit_move (dest, XEXP (XEXP (src, 0), 0));
+      riscv_legitimize_poly_move (mode, dest_tmp, tmp, XEXP (XEXP (src, 
0), 1));