diff mbox

[MIPS] Target flag and build option to disable indexed memory OPs.

Message ID 6d536359-e7a9-a13c-59db-d7a21e61ed0c@imgtec.com
State New
Headers show

Commit Message

Doug Gilmore Jan. 14, 2017, 12:25 a.m. UTC 
I recently bisected PR78176 to problems introduced with r21650.

Given the short time until the release, we would like to 
provide a target flag and build option to avoid the bug until
we are able to resolve the problem with the commit.  Note that
as Matthew Fortune has mentioned in the PR:

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78176#c5

the problem could also be addressed by updates to the Linux kernel
since the problem is only exposed by running MIPS 32-bit binaries on
64-bit kernels.

Bootstrapped on X86_64, regression tested on X86_64 and MIPS.

OK to commit?

Thanks,

Doug

Comments

Matthew Fortune Jan. 16, 2017, 4:25 p.m. UTC | #1 
Doug Gilmore <Doug.Gilmore@imgtec.com>
> I recently bisected PR78176 to problems introduced with r21650.

> 

> Given the short time until the release, we would like to provide a

> target flag and build option to avoid the bug until we are able to

> resolve the problem with the commit.  Note that as Matthew Fortune has

> mentioned in the PR:

> 

> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78176#c5

> 

> the problem could also be addressed by updates to the Linux kernel since

> the problem is only exposed by running MIPS 32-bit binaries on 64-bit

> kernels.

> 

> Bootstrapped on X86_64, regression tested on X86_64 and MIPS.

> 

> OK to commit?


Given this is a generic reference to indexed load/store and the issue could
affect any indexed operation then I think it needs to include all of the
following as well:

/* ISA has lwxs instruction (load w/scaled index address.  */
#define ISA_HAS_LWXS            ((TARGET_SMARTMIPS || TARGET_MICROMIPS) \
                                 && !TARGET_MIPS16)

/* ISA has lbx, lbux, lhx, lhx, lhux, lwx, lwux, or ldx instruction. */
#define ISA_HAS_LBX             (TARGET_OCTEON2)
#define ISA_HAS_LBUX            (ISA_HAS_DSP || TARGET_OCTEON2)
#define ISA_HAS_LHX             (ISA_HAS_DSP || TARGET_OCTEON2)
#define ISA_HAS_LHUX            (TARGET_OCTEON2)
#define ISA_HAS_LWX             (ISA_HAS_DSP || TARGET_OCTEON2)
#define ISA_HAS_LWUX            (TARGET_OCTEON2 && TARGET_64BIT)
#define ISA_HAS_LDX             ((ISA_HAS_DSP || TARGET_OCTEON2) \
                                 && TARGET_64BIT)

The DSP LBUX/LHX/LWX/LDX intrinsics will also need a new AVAIL predicate
to disable them. The snag is that some DSP code will fail to compile if it
uses the DSP load intrinsics directly.

I see no way of avoiding that. Therefore, distributions that use
--without-indexed-load-store will have to cope with some potential DSP
fallout if they enable DSP at all.

@Catherine: I'd like your input here if possible as I advocated this
approach, comments on option names welcome too.  I quite like the verbose
name.

@Doug: Have you tried running the testsuite with the configure option
--without-indexed-load-store? There may be tests that need adjusting where they
test indexed load/store. We probably need a pre-processor macro
to detect if the option is enabled/disabled so that DSP code can be predicated
on indexed load being available.

Thanks,
Matthew
Moore, Catherine Jan. 17, 2017, 12:01 a.m. UTC | #2 
> -----Original Message-----

> From: gcc-patches-owner@gcc.gnu.org [mailto:gcc-patches-

> owner@gcc.gnu.org] On Behalf Of Matthew Fortune

> Sent: Monday, January 16, 2017 11:25 AM

> To: Doug Gilmore <Doug.Gilmore@imgtec.com>; gcc-

> patches@gcc.gnu.org

> Cc: Moore, Catherine <Catherine_Moore@mentor.com>

> Subject: RE: [PATCH, MIPS] Target flag and build option to disable

> indexed memory OPs.

> 

> Doug Gilmore <Doug.Gilmore@imgtec.com>

> > I recently bisected PR78176 to problems introduced with r21650.

> >

> > Given the short time until the release, we would like to provide a

> > target flag and build option to avoid the bug until we are able to

> > resolve the problem with the commit.  Note that as Matthew Fortune

> has

> > mentioned in the PR:

> >

> > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78176#c5

> >

> > the problem could also be addressed by updates to the Linux kernel

> since

> > the problem is only exposed by running MIPS 32-bit binaries on 64-

> bit

> > kernels.

> >

> > Bootstrapped on X86_64, regression tested on X86_64 and MIPS.

> >

> > OK to commit?

> 

> Given this is a generic reference to indexed load/store and the issue

> could

> affect any indexed operation then I think it needs to include all of the

> following as well:

> 

> /* ISA has lwxs instruction (load w/scaled index address.  */

> #define ISA_HAS_LWXS            ((TARGET_SMARTMIPS ||

> TARGET_MICROMIPS) \

>                                  && !TARGET_MIPS16)

> 

> /* ISA has lbx, lbux, lhx, lhx, lhux, lwx, lwux, or ldx instruction. */

> #define ISA_HAS_LBX             (TARGET_OCTEON2)

> #define ISA_HAS_LBUX            (ISA_HAS_DSP || TARGET_OCTEON2)

> #define ISA_HAS_LHX             (ISA_HAS_DSP || TARGET_OCTEON2)

> #define ISA_HAS_LHUX            (TARGET_OCTEON2)

> #define ISA_HAS_LWX             (ISA_HAS_DSP || TARGET_OCTEON2)

> #define ISA_HAS_LWUX            (TARGET_OCTEON2 && TARGET_64BIT)

> #define ISA_HAS_LDX             ((ISA_HAS_DSP || TARGET_OCTEON2) \

>                                  && TARGET_64BIT)

> 

> The DSP LBUX/LHX/LWX/LDX intrinsics will also need a new AVAIL

> predicate

> to disable them. The snag is that some DSP code will fail to compile if it

> uses the DSP load intrinsics directly.

> 

> I see no way of avoiding that. Therefore, distributions that use

> --without-indexed-load-store will have to cope with some potential

> DSP

> fallout if they enable DSP at all.

> 

> @Catherine: I'd like your input here if possible as I advocated this

> approach, comments on option names welcome too.  I quite like the

> verbose

> name.


Okay, based on my reading of the comments in the bug report, you are proposing this option as a workaround to a kernel deficiency.  I don't see any agreement that this is actually a compiler bug.
Do we really need to include the DSP instrinsics as well?   Do you think that many distributions actually enable DSP?  

The option name itself is acceptable to me.  I'd like to see documentation that explains when this problem is exposed.  I'd like to limit the fix to LWXS and I'd like to see the testcase from the bug report added to the testsuite.
I also agree that the preprocessor macro is a good idea (even if we decide to forgo the DSP portion of the patch).

Catherine

> 

> @Doug: Have you tried running the testsuite with the configure option

> --without-indexed-load-store? There may be tests that need adjusting

> where they

> test indexed load/store. We probably need a pre-processor macro

> to detect if the option is enabled/disabled so that DSP code can be

> predicated

> on indexed load being available.

> 

> Thanks,

> Matthew
Matthew Fortune Jan. 17, 2017, 9:34 a.m. UTC | #3 
Moore, Catherine <Catherine_Moore@mentor.com> writes:
> > -----Original Message-----

> > From: gcc-patches-owner@gcc.gnu.org [mailto:gcc-patches-

> > owner@gcc.gnu.org] On Behalf Of Matthew Fortune

> > Sent: Monday, January 16, 2017 11:25 AM

> > To: Doug Gilmore <Doug.Gilmore@imgtec.com>; gcc-

> > patches@gcc.gnu.org

> > Cc: Moore, Catherine <Catherine_Moore@mentor.com>

> > Subject: RE: [PATCH, MIPS] Target flag and build option to disable

> > indexed memory OPs.

> >

> > Doug Gilmore <Doug.Gilmore@imgtec.com>

> > > I recently bisected PR78176 to problems introduced with r21650.

> > >

> > > Given the short time until the release, we would like to provide a

> > > target flag and build option to avoid the bug until we are able to

> > > resolve the problem with the commit.  Note that as Matthew Fortune

> > has

> > > mentioned in the PR:

> > >

> > > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78176#c5

> > >

> > > the problem could also be addressed by updates to the Linux kernel

> > since

> > > the problem is only exposed by running MIPS 32-bit binaries on 64-

> > bit

> > > kernels.

> > >

> > > Bootstrapped on X86_64, regression tested on X86_64 and MIPS.

> > >

> > > OK to commit?

> >

> > Given this is a generic reference to indexed load/store and the issue

> > could

> > affect any indexed operation then I think it needs to include all of the

> > following as well:

> >

> > /* ISA has lwxs instruction (load w/scaled index address.  */

> > #define ISA_HAS_LWXS            ((TARGET_SMARTMIPS ||

> > TARGET_MICROMIPS) \

> >                                  && !TARGET_MIPS16)

> >

> > /* ISA has lbx, lbux, lhx, lhx, lhux, lwx, lwux, or ldx instruction. */

> > #define ISA_HAS_LBX             (TARGET_OCTEON2)

> > #define ISA_HAS_LBUX            (ISA_HAS_DSP || TARGET_OCTEON2)

> > #define ISA_HAS_LHX             (ISA_HAS_DSP || TARGET_OCTEON2)

> > #define ISA_HAS_LHUX            (TARGET_OCTEON2)

> > #define ISA_HAS_LWX             (ISA_HAS_DSP || TARGET_OCTEON2)

> > #define ISA_HAS_LWUX            (TARGET_OCTEON2 && TARGET_64BIT)

> > #define ISA_HAS_LDX             ((ISA_HAS_DSP || TARGET_OCTEON2) \

> >                                  && TARGET_64BIT)

> >

> > The DSP LBUX/LHX/LWX/LDX intrinsics will also need a new AVAIL

> > predicate

> > to disable them. The snag is that some DSP code will fail to compile if it

> > uses the DSP load intrinsics directly.

> >

> > I see no way of avoiding that. Therefore, distributions that use

> > --without-indexed-load-store will have to cope with some potential

> > DSP

> > fallout if they enable DSP at all.

> >

> > @Catherine: I'd like your input here if possible as I advocated this

> > approach, comments on option names welcome too.  I quite like the

> > verbose

> > name.

> 

> Okay, based on my reading of the comments in the bug report, you are proposing this option

> as a workaround to a kernel deficiency.  I don't see any agreement that this is actually a

> compiler bug.

> Do we really need to include the DSP instrinsics as well?   Do you think that many

> distributions actually enable DSP?

> 

> The option name itself is acceptable to me.  I'd like to see documentation that explains

> when this problem is exposed.  I'd like to limit the fix to LWXS and I'd like to see the

> testcase from the bug report added to the testsuite.

> I also agree that the preprocessor macro is a good idea (even if we decide to forgo the

> DSP portion of the patch).


Thanks for the comments.

Having thought further I agree we can safely ignore DSP indexed load and micromips LWXS on
the basis that DSP code will not run on a MIPS64 processor anyway (at least none that I
know of) so the issue cannot occur and similarly for microMIPS, there are no 64-bit cores.

Restricting to just LWXC1/SWXC1/LDXC1/SDXC1 is therefore fine but we should reflect
that in option names then.

--with-lxc1-sxc1 --without-lxc1-sxc1
-mlxc1-sxc1

These names reflect the internal macro that controls availability of these instructions.

Macro name: __mips_no_lxc1_sxc1
Defined when !ISA_HAS_LXC1_SXC1 so would be present even when targeting a core that
doesn't have the instructions anyway.

Any refinements to this Catherine?

Thanks,
Matthew
Moore, Catherine Jan. 17, 2017, 1:41 p.m. UTC | #4 
> -----Original Message-----

> From: Matthew Fortune [mailto:Matthew.Fortune@imgtec.com]

> Sent: Tuesday, January 17, 2017 4:35 AM

> To: Moore, Catherine <Catherine_Moore@mentor.com>; Doug

> Gilmore <Doug.Gilmore@imgtec.com>; gcc-patches@gcc.gnu.org

> Subject: RE: [PATCH, MIPS] Target flag and build option to disable

> indexed memory OPs.

> 

> Moore, Catherine <Catherine_Moore@mentor.com> writes:

> > > -----Original Message-----

> > > From: gcc-patches-owner@gcc.gnu.org [mailto:gcc-patches-

> > > owner@gcc.gnu.org] On Behalf Of Matthew Fortune

> > > Sent: Monday, January 16, 2017 11:25 AM

> > > To: Doug Gilmore <Doug.Gilmore@imgtec.com>; gcc-

> > > patches@gcc.gnu.org

> > > Cc: Moore, Catherine <Catherine_Moore@mentor.com>

> > > Subject: RE: [PATCH, MIPS] Target flag and build option to disable

> > > indexed memory OPs.

> > >

> > > Doug Gilmore <Doug.Gilmore@imgtec.com>

> > > > I recently bisected PR78176 to problems introduced with r21650.

> > > >

> > > > Given the short time until the release, we would like to provide a

> > > > target flag and build option to avoid the bug until we are able to

> > > > resolve the problem with the commit.  Note that as Matthew

> Fortune

> > > has

> > > > mentioned in the PR:

> > > >

> > > > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78176#c5

> > > >

> > > > the problem could also be addressed by updates to the Linux

> kernel

> > > since

> > > > the problem is only exposed by running MIPS 32-bit binaries on

> 64-

> > > bit

> > > > kernels.

> > > >

> > > > Bootstrapped on X86_64, regression tested on X86_64 and MIPS.

> > > >

> > > > OK to commit?

> > >

> > > Given this is a generic reference to indexed load/store and the

> issue

> > > could

> > > affect any indexed operation then I think it needs to include all of

> the

> > > following as well:

> > >

> > > /* ISA has lwxs instruction (load w/scaled index address.  */

> > > #define ISA_HAS_LWXS            ((TARGET_SMARTMIPS ||

> > > TARGET_MICROMIPS) \

> > >                                  && !TARGET_MIPS16)

> > >

> > > /* ISA has lbx, lbux, lhx, lhx, lhux, lwx, lwux, or ldx instruction. */

> > > #define ISA_HAS_LBX             (TARGET_OCTEON2)

> > > #define ISA_HAS_LBUX            (ISA_HAS_DSP || TARGET_OCTEON2)

> > > #define ISA_HAS_LHX             (ISA_HAS_DSP || TARGET_OCTEON2)

> > > #define ISA_HAS_LHUX            (TARGET_OCTEON2)

> > > #define ISA_HAS_LWX             (ISA_HAS_DSP || TARGET_OCTEON2)

> > > #define ISA_HAS_LWUX            (TARGET_OCTEON2 &&

> TARGET_64BIT)

> > > #define ISA_HAS_LDX             ((ISA_HAS_DSP || TARGET_OCTEON2)

> \

> > >                                  && TARGET_64BIT)

> > >

> > > The DSP LBUX/LHX/LWX/LDX intrinsics will also need a new AVAIL

> > > predicate

> > > to disable them. The snag is that some DSP code will fail to compile

> if it

> > > uses the DSP load intrinsics directly.

> > >

> > > I see no way of avoiding that. Therefore, distributions that use

> > > --without-indexed-load-store will have to cope with some potential

> > > DSP

> > > fallout if they enable DSP at all.

> > >

> > > @Catherine: I'd like your input here if possible as I advocated this

> > > approach, comments on option names welcome too.  I quite like

> the

> > > verbose

> > > name.

> >

> > Okay, based on my reading of the comments in the bug report, you

> are proposing this option

> > as a workaround to a kernel deficiency.  I don't see any agreement

> that this is actually a

> > compiler bug.

> > Do we really need to include the DSP instrinsics as well?   Do you

> think that many

> > distributions actually enable DSP?

> >

> > The option name itself is acceptable to me.  I'd like to see

> documentation that explains

> > when this problem is exposed.  I'd like to limit the fix to LWXS and I'd

> like to see the

> > testcase from the bug report added to the testsuite.

> > I also agree that the preprocessor macro is a good idea (even if we

> decide to forgo the

> > DSP portion of the patch).

> 

> Thanks for the comments.

> 

> Having thought further I agree we can safely ignore DSP indexed load

> and micromips LWXS on

> the basis that DSP code will not run on a MIPS64 processor anyway (at

> least none that I

> know of) so the issue cannot occur and similarly for microMIPS, there

> are no 64-bit cores.

> 

> Restricting to just LWXC1/SWXC1/LDXC1/SDXC1 is therefore fine but

> we should reflect

> that in option names then.

> 

> --with-lxc1-sxc1 --without-lxc1-sxc1

> -mlxc1-sxc1

> 

> These names reflect the internal macro that controls availability of

> these instructions.

> 

> Macro name: __mips_no_lxc1_sxc1

> Defined when !ISA_HAS_LXC1_SXC1 so would be present even when

> targeting a core that

> doesn't have the instructions anyway.

> 

> Any refinements to this Catherine?

> 

No.  This plan looks good.
Doug Gilmore Jan. 18, 2017, 12:10 a.m. UTC | #5 
On 01/17/2017 05:41 AM, Moore, Catherine wrote:
> 
>
>> ...
>> Having thought further I agree we can safely ignore DSP indexed load
>> and micromips LWXS on
>> the basis that DSP code will not run on a MIPS64 processor anyway (at
>> least none that I
>> know of) so the issue cannot occur and similarly for microMIPS, there
>> are no 64-bit cores.
>>
>> Restricting to just LWXC1/SWXC1/LDXC1/SDXC1 is therefore fine but
>> we should reflect
>> that in option names then.
>>
>> --with-lxc1-sxc1 --without-lxc1-sxc1
>> -mlxc1-sxc1
>>
>> These names reflect the internal macro that controls availability of
>> these instructions.
>>
>> Macro name: __mips_no_lxc1_sxc1
>> Defined when !ISA_HAS_LXC1_SXC1 so would be present even when
>> targeting a core that
>> doesn't have the instructions anyway.
>>
>> Any refinements to this Catherine?
>>
> No.  This plan looks good.
> 
Sounds good, I'll update the patch accordingly.

BTW, if we did guard all of the indexed memory OPs with a flag
there would be ~150 tests to clean up when configuring with indexed
memory OPs disabled.  When I tested with indexed memory OPs disabled
with the original patch, there were no additional regressions.

Also I'll be updating the bug report with my current take on what went
wrong with r216501.

Thanks,

Doug
diff mbox

Patch

From 2a6b11b30ff335ea8e669ae8d3f1bd531ac5b8d3 Mon Sep 17 00:00:00 2001
From: Doug Gilmore <doug.gilmore@imgtec.com>
Date: Wed, 11 Jan 2017 16:49:27 -0800
Subject: [PATCH] [MIPS] PR target/78176 add -mindexed-load-store.

	PR target/78176
	* config.gcc (supported_defaults): Add indexed-load-store.
	(with_indexed_load_store): Add validation.
	(all_defaults): Add indexed-load-store.
	* config/mips/mips.opt (mindexed-load-store): New option.
	* gcc/config/mips/mips.h (OPTION_DEFAULT_SPECS): Add a default for
	mindexed-load-store.
	ISA_HAS_LXC1_SXC1 gate with mips_indexed_load_store.
	* gcc/doc/invoke.texi (-mindexed-load-store): Document the new option.
	* doc/install.texi (--with-indexed-load-store): Document the new option.
---
 gcc/config.gcc           | 19 +++++++++++++++++--
 gcc/config/mips/mips.h   |  6 ++++--
 gcc/config/mips/mips.opt |  4 ++++
 gcc/doc/install.texi     |  8 ++++++++
 gcc/doc/invoke.texi      |  6 ++++++
 5 files changed, 39 insertions(+), 4 deletions(-)

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 7c27546..e712599 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -3940,7 +3940,7 @@  case "${target}" in
 		;;
 
 	mips*-*-*)
-		supported_defaults="abi arch arch_32 arch_64 float fpu nan fp_32 odd_spreg_32 tune tune_32 tune_64 divide llsc mips-plt synci"
+		supported_defaults="abi arch arch_32 arch_64 float fpu nan fp_32 odd_spreg_32 tune tune_32 tune_64 divide llsc mips-plt synci indexed-load-store"
 
 		case ${with_float} in
 		"" | soft | hard)
@@ -4063,6 +4063,21 @@  case "${target}" in
 			exit 1
 			;;
 		esac
+
+		case ${with_indexed_load_store} in
+		yes)
+			with_indexed_load_store=indexed-load-store
+			;;
+		no)
+			with_indexed_load_store=no-indexed-load-store
+			;;
+		"")
+			;;
+		*)
+			echo "Unknown indexed-load-store type used in --with-indexed-load-store" 1>&2
+			exit 1
+			;;
+		esac
 		;;
 
 	nds32*-*-*)
@@ -4496,7 +4511,7 @@  case ${target} in
 esac
 
 t=
-all_defaults="abi cpu cpu_32 cpu_64 arch arch_32 arch_64 tune tune_32 tune_64 schedule float mode fpu nan fp_32 odd_spreg_32 divide llsc mips-plt synci tls"
+all_defaults="abi cpu cpu_32 cpu_64 arch arch_32 arch_64 tune tune_32 tune_64 schedule float mode fpu nan fp_32 odd_spreg_32 divide llsc mips-plt synci tls indexed-load-store"
 for option in $all_defaults
 do
 	eval "val=\$with_"`echo $option | sed s/-/_/g`
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index f91b43d..6d2aa9a 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -866,7 +866,8 @@  struct mips_cpu_info {
   {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
   {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
   {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
-  {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }
+  {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" },			\
+  {"indexed-load-store", "%{!mindexed-load-store:%{!mno-indexed-load-store:-m%(VALUE)}}" } \
 
 /* A spec that infers the:
    -mnan=2008 setting from a -mips argument,
@@ -1030,7 +1031,8 @@  struct mips_cpu_info {
 
 /* ISA has floating-point indexed load and store instructions
    (LWXC1, LDXC1, SWXC1 and SDXC1).  */
-#define ISA_HAS_LXC1_SXC1	ISA_HAS_FP4
+#define ISA_HAS_LXC1_SXC1	(ISA_HAS_FP4				\
+				 && mips_indexed_load_store)
 
 /* ISA has paired-single instructions.  */
 #define ISA_HAS_PAIRED_SINGLE	((ISA_MIPS64				\
diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt
index 2559649..ae1e4cf 100644
--- a/gcc/config/mips/mips.opt
+++ b/gcc/config/mips/mips.opt
@@ -388,6 +388,10 @@  mlra
 Target Report Var(mips_lra_flag) Init(1) Save
 Use LRA instead of reload.
 
+mindexed-load-store
+Target Report Var(mips_indexed_load_store) Init(1)
+Use index memory Ops where applicable.
+
 mtune=
 Target RejectNegative Joined Var(mips_tune_option) ToLower Enum(mips_arch_opt_value)
 -mtune=PROCESSOR	Optimize the output for PROCESSOR.
diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi
index 4958773..ff91879 100644
--- a/gcc/doc/install.texi
+++ b/gcc/doc/install.texi
@@ -1371,6 +1371,14 @@  On MIPS targets, make @option{-msynci} the default when no
 On MIPS targets, make @option{-mno-synci} the default when no
 @option{-msynci} option is passed.  This is the default.
 
+@item --with-indexed-load-store
+On MIPS targets, make @option{-mindexed-load-store} the default when no
+@option{-mno-indexed-load-store} option is passed.  This is the default.
+
+@item --without-indexed-load-store
+On MIPS targets, make @option{-mno-indexed-load-store} the default when no
+@option{-mindexed-load-store} option is passed.
+
 @item --with-mips-plt
 On MIPS targets, make use of copy relocations and PLTs.
 These features are extensions to the traditional
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 2bd105a..75e860e 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -19856,6 +19856,12 @@  it is unused.
 
 This optimization is off by default at all optimization levels.
 
+@item -mindexed-load-store
+@itemx -mno-indexed-load-store
+@opindex mindexed-load-store
+When applicable, enable (disable) the generation of indexed memory
+instructions.  Enabled by default.
+
 @end table
 
 @node MMIX Options
-- 
1.9.1