From 2a6b11b30ff335ea8e669ae8d3f1bd531ac5b8d3 Mon Sep 17 00:00:00 2001
From: Doug Gilmore <doug.gilmore@imgtec.com>
Date: Wed, 11 Jan 2017 16:49:27 -0800
Subject: [PATCH] [MIPS] PR target/78176 add -mindexed-load-store.

	PR target/78176
	* config.gcc (supported_defaults): Add indexed-load-store.
	(with_indexed_load_store): Add validation.
	(all_defaults): Add indexed-load-store.
	* config/mips/mips.opt (mindexed-load-store): New option.
	* gcc/config/mips/mips.h (OPTION_DEFAULT_SPECS): Add a default for
	mindexed-load-store.
	ISA_HAS_LXC1_SXC1 gate with mips_indexed_load_store.
	* gcc/doc/invoke.texi (-mindexed-load-store): Document the new option.
	* doc/install.texi (--with-indexed-load-store): Document the new option.
---
 gcc/config.gcc           | 19 +++++++++++++++++--
 gcc/config/mips/mips.h   |  6 ++++--
 gcc/config/mips/mips.opt |  4 ++++
 gcc/doc/install.texi     |  8 ++++++++
 gcc/doc/invoke.texi      |  6 ++++++
 5 files changed, 39 insertions(+), 4 deletions(-)

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 7c27546..e712599 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -3940,7 +3940,7 @@ case "${target}" in
 		;;
 
 	mips*-*-*)
-		supported_defaults="abi arch arch_32 arch_64 float fpu nan fp_32 odd_spreg_32 tune tune_32 tune_64 divide llsc mips-plt synci"
+		supported_defaults="abi arch arch_32 arch_64 float fpu nan fp_32 odd_spreg_32 tune tune_32 tune_64 divide llsc mips-plt synci indexed-load-store"
 
 		case ${with_float} in
 		"" | soft | hard)
@@ -4063,6 +4063,21 @@ case "${target}" in
 			exit 1
 			;;
 		esac
+
+		case ${with_indexed_load_store} in
+		yes)
+			with_indexed_load_store=indexed-load-store
+			;;
+		no)
+			with_indexed_load_store=no-indexed-load-store
+			;;
+		"")
+			;;
+		*)
+			echo "Unknown indexed-load-store type used in --with-indexed-load-store" 1>&2
+			exit 1
+			;;
+		esac
 		;;
 
 	nds32*-*-*)
@@ -4496,7 +4511,7 @@ case ${target} in
 esac
 
 t=
-all_defaults="abi cpu cpu_32 cpu_64 arch arch_32 arch_64 tune tune_32 tune_64 schedule float mode fpu nan fp_32 odd_spreg_32 divide llsc mips-plt synci tls"
+all_defaults="abi cpu cpu_32 cpu_64 arch arch_32 arch_64 tune tune_32 tune_64 schedule float mode fpu nan fp_32 odd_spreg_32 divide llsc mips-plt synci tls indexed-load-store"
 for option in $all_defaults
 do
 	eval "val=\$with_"`echo $option | sed s/-/_/g`
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index f91b43d..6d2aa9a 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -866,7 +866,8 @@ struct mips_cpu_info {
   {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
   {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
   {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
-  {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }
+  {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" },			\
+  {"indexed-load-store", "%{!mindexed-load-store:%{!mno-indexed-load-store:-m%(VALUE)}}" } \
 
 /* A spec that infers the:
    -mnan=2008 setting from a -mips argument,
@@ -1030,7 +1031,8 @@ struct mips_cpu_info {
 
 /* ISA has floating-point indexed load and store instructions
    (LWXC1, LDXC1, SWXC1 and SDXC1).  */
-#define ISA_HAS_LXC1_SXC1	ISA_HAS_FP4
+#define ISA_HAS_LXC1_SXC1	(ISA_HAS_FP4				\
+				 && mips_indexed_load_store)
 
 /* ISA has paired-single instructions.  */
 #define ISA_HAS_PAIRED_SINGLE	((ISA_MIPS64				\
diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt
index 2559649..ae1e4cf 100644
--- a/gcc/config/mips/mips.opt
+++ b/gcc/config/mips/mips.opt
@@ -388,6 +388,10 @@ mlra
 Target Report Var(mips_lra_flag) Init(1) Save
 Use LRA instead of reload.
 
+mindexed-load-store
+Target Report Var(mips_indexed_load_store) Init(1)
+Use index memory Ops where applicable.
+
 mtune=
 Target RejectNegative Joined Var(mips_tune_option) ToLower Enum(mips_arch_opt_value)
 -mtune=PROCESSOR	Optimize the output for PROCESSOR.
diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi
index 4958773..ff91879 100644
--- a/gcc/doc/install.texi
+++ b/gcc/doc/install.texi
@@ -1371,6 +1371,14 @@ On MIPS targets, make @option{-msynci} the default when no
 On MIPS targets, make @option{-mno-synci} the default when no
 @option{-msynci} option is passed.  This is the default.
 
+@item --with-indexed-load-store
+On MIPS targets, make @option{-mindexed-load-store} the default when no
+@option{-mno-indexed-load-store} option is passed.  This is the default.
+
+@item --without-indexed-load-store
+On MIPS targets, make @option{-mno-indexed-load-store} the default when no
+@option{-mindexed-load-store} option is passed.
+
 @item --with-mips-plt
 On MIPS targets, make use of copy relocations and PLTs.
 These features are extensions to the traditional
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 2bd105a..75e860e 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -19856,6 +19856,12 @@ it is unused.
 
 This optimization is off by default at all optimization levels.
 
+@item -mindexed-load-store
+@itemx -mno-indexed-load-store
+@opindex mindexed-load-store
+When applicable, enable (disable) the generation of indexed memory
+instructions.  Enabled by default.
+
 @end table
 
 @node MMIX Options
-- 
1.9.1

