From patchwork Sat Jan 14 00:25:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Gilmore X-Patchwork-Id: 715306 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3v0gJt0gD7z9vF3 for ; Sat, 14 Jan 2017 11:25:56 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="r+No4ED3"; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to :from:subject:message-id:date:mime-version:content-type; q=dns; s=default; b=Rf9+vpHEzcbeOD43+EpFE2MYikF0SLSqEKW1OHd52dnS3ukdbM 0PyCy8bZDF/ptq+IeZMwW4E/qdnKQyrnnUwBghxjYhVXcsmCOBP5KYIGHrtzNjpT QMowIfj2vhtGv8BO623Di4q9ZWZKV67pfog7dqAHrfs0RCxBffhCU2G9M= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to :from:subject:message-id:date:mime-version:content-type; s= default; bh=1D+2Y3mMm2ID2US4qG39vEfbxWY=; b=r+No4ED3M3pEMKPA9Grd 4GsL5C9v89aj3GbWw7sDtt1XJQduNSHxiNPYTSuZUAMW5wDj++7FbIV+etLvRlgX uURC+FaoPx5mRiuYVH8nJ8t54SMVMhXGQ6TsWLPT7D8EtZGNtt1sxLYe3KcbXa/x TGco+eZvYgLKEdjf4gyyJcU= Received: (qmail 101026 invoked by alias); 14 Jan 2017 00:25:49 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 101001 invoked by uid 89); 14 Jan 2017 00:25:45 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-3.6 required=5.0 tests=AWL, BAYES_00, KAM_WEIRDTRICK1, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, SPF_PASS autolearn=ham version=3.3.2 spammy=1.9.1 X-HELO: mailapp01.imgtec.com Received: from mailapp01.imgtec.com (HELO mailapp01.imgtec.com) (195.59.15.196) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sat, 14 Jan 2017 00:25:34 +0000 Received: from hhmail02.hh.imgtec.org (unknown [10.100.10.20]) by Forcepoint Email with ESMTPS id AE95D80985116 for ; Sat, 14 Jan 2017 00:25:26 +0000 (GMT) Received: from BAMAIL02.ba.imgtec.org (10.20.40.28) by hhmail02.hh.imgtec.org (10.100.10.20) with Microsoft SMTP Server (TLS) id 14.3.294.0; Sat, 14 Jan 2017 00:25:31 +0000 Received: from [10.20.2.42] (10.20.2.42) by bamail02.ba.imgtec.org (10.20.40.28) with Microsoft SMTP Server id 14.3.266.1; Fri, 13 Jan 2017 16:25:29 -0800 To: , From: Doug Gilmore Subject: [PATCH, MIPS] Target flag and build option to disable indexed memory OPs. Message-ID: <6d536359-e7a9-a13c-59db-d7a21e61ed0c@imgtec.com> Date: Fri, 13 Jan 2017 16:25:29 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.4.0 MIME-Version: 1.0 I recently bisected PR78176 to problems introduced with r21650. Given the short time until the release, we would like to provide a target flag and build option to avoid the bug until we are able to resolve the problem with the commit. Note that as Matthew Fortune has mentioned in the PR: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78176#c5 the problem could also be addressed by updates to the Linux kernel since the problem is only exposed by running MIPS 32-bit binaries on 64-bit kernels. Bootstrapped on X86_64, regression tested on X86_64 and MIPS. OK to commit? Thanks, Doug From 2a6b11b30ff335ea8e669ae8d3f1bd531ac5b8d3 Mon Sep 17 00:00:00 2001 From: Doug Gilmore Date: Wed, 11 Jan 2017 16:49:27 -0800 Subject: [PATCH] [MIPS] PR target/78176 add -mindexed-load-store. PR target/78176 * config.gcc (supported_defaults): Add indexed-load-store. (with_indexed_load_store): Add validation. (all_defaults): Add indexed-load-store. * config/mips/mips.opt (mindexed-load-store): New option. * gcc/config/mips/mips.h (OPTION_DEFAULT_SPECS): Add a default for mindexed-load-store. ISA_HAS_LXC1_SXC1 gate with mips_indexed_load_store. * gcc/doc/invoke.texi (-mindexed-load-store): Document the new option. * doc/install.texi (--with-indexed-load-store): Document the new option. --- gcc/config.gcc | 19 +++++++++++++++++-- gcc/config/mips/mips.h | 6 ++++-- gcc/config/mips/mips.opt | 4 ++++ gcc/doc/install.texi | 8 ++++++++ gcc/doc/invoke.texi | 6 ++++++ 5 files changed, 39 insertions(+), 4 deletions(-) diff --git a/gcc/config.gcc b/gcc/config.gcc index 7c27546..e712599 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -3940,7 +3940,7 @@ case "${target}" in ;; mips*-*-*) - supported_defaults="abi arch arch_32 arch_64 float fpu nan fp_32 odd_spreg_32 tune tune_32 tune_64 divide llsc mips-plt synci" + supported_defaults="abi arch arch_32 arch_64 float fpu nan fp_32 odd_spreg_32 tune tune_32 tune_64 divide llsc mips-plt synci indexed-load-store" case ${with_float} in "" | soft | hard) @@ -4063,6 +4063,21 @@ case "${target}" in exit 1 ;; esac + + case ${with_indexed_load_store} in + yes) + with_indexed_load_store=indexed-load-store + ;; + no) + with_indexed_load_store=no-indexed-load-store + ;; + "") + ;; + *) + echo "Unknown indexed-load-store type used in --with-indexed-load-store" 1>&2 + exit 1 + ;; + esac ;; nds32*-*-*) @@ -4496,7 +4511,7 @@ case ${target} in esac t= -all_defaults="abi cpu cpu_32 cpu_64 arch arch_32 arch_64 tune tune_32 tune_64 schedule float mode fpu nan fp_32 odd_spreg_32 divide llsc mips-plt synci tls" +all_defaults="abi cpu cpu_32 cpu_64 arch arch_32 arch_64 tune tune_32 tune_64 schedule float mode fpu nan fp_32 odd_spreg_32 divide llsc mips-plt synci tls indexed-load-store" for option in $all_defaults do eval "val=\$with_"`echo $option | sed s/-/_/g` diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index f91b43d..6d2aa9a 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -866,7 +866,8 @@ struct mips_cpu_info { {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \ {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \ {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \ - {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" } + {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }, \ + {"indexed-load-store", "%{!mindexed-load-store:%{!mno-indexed-load-store:-m%(VALUE)}}" } \ /* A spec that infers the: -mnan=2008 setting from a -mips argument, @@ -1030,7 +1031,8 @@ struct mips_cpu_info { /* ISA has floating-point indexed load and store instructions (LWXC1, LDXC1, SWXC1 and SDXC1). */ -#define ISA_HAS_LXC1_SXC1 ISA_HAS_FP4 +#define ISA_HAS_LXC1_SXC1 (ISA_HAS_FP4 \ + && mips_indexed_load_store) /* ISA has paired-single instructions. */ #define ISA_HAS_PAIRED_SINGLE ((ISA_MIPS64 \ diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt index 2559649..ae1e4cf 100644 --- a/gcc/config/mips/mips.opt +++ b/gcc/config/mips/mips.opt @@ -388,6 +388,10 @@ mlra Target Report Var(mips_lra_flag) Init(1) Save Use LRA instead of reload. +mindexed-load-store +Target Report Var(mips_indexed_load_store) Init(1) +Use index memory Ops where applicable. + mtune= Target RejectNegative Joined Var(mips_tune_option) ToLower Enum(mips_arch_opt_value) -mtune=PROCESSOR Optimize the output for PROCESSOR. diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi index 4958773..ff91879 100644 --- a/gcc/doc/install.texi +++ b/gcc/doc/install.texi @@ -1371,6 +1371,14 @@ On MIPS targets, make @option{-msynci} the default when no On MIPS targets, make @option{-mno-synci} the default when no @option{-msynci} option is passed. This is the default. +@item --with-indexed-load-store +On MIPS targets, make @option{-mindexed-load-store} the default when no +@option{-mno-indexed-load-store} option is passed. This is the default. + +@item --without-indexed-load-store +On MIPS targets, make @option{-mno-indexed-load-store} the default when no +@option{-mindexed-load-store} option is passed. + @item --with-mips-plt On MIPS targets, make use of copy relocations and PLTs. These features are extensions to the traditional diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 2bd105a..75e860e 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -19856,6 +19856,12 @@ it is unused. This optimization is off by default at all optimization levels. +@item -mindexed-load-store +@itemx -mno-indexed-load-store +@opindex mindexed-load-store +When applicable, enable (disable) the generation of indexed memory +instructions. Enabled by default. + @end table @node MMIX Options -- 1.9.1