diff mbox series

[v2,3/3] RISC-V: Add support for XCVbi extension in CV32E40P

Message ID 20231113133530.1727444-4-mary.bennett@embecosm.com
State New
Headers show
Series RISC-V: Support CORE-V XCVELW and XCVBI extensions | expand

Commit Message

Mary Bennett Nov. 13, 2023, 1:35 p.m. UTC 
Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

Contributors:
  Mary Bennett <mary.bennett@embecosm.com>
  Nandni Jamnadas <nandni.jamnadas@embecosm.com>
  Pietra Ferreira <pietra.ferreira@embecosm.com>
  Charlie Keaney
  Jessica Mills
  Craig Blackmore <craig.blackmore@embecosm.com>
  Simon Cook <simon.cook@embecosm.com>
  Jeremy Bennett <jeremy.bennett@embecosm.com>
  Helene Chelin <helene.chelin@embecosm.com>

gcc/ChangeLog:
	* common/config/riscv/riscv-common.cc: Create XCVbi extension
	  support.
	* config/riscv/riscv.opt: Likewise.
	* config/riscv/corev.md: Implement cv_branch<mode> pattern
	  for cv.beqimm and cv.bneimm.
	* config/riscv/riscv.md: Change pattern priority so corev.md
	  patterns run before riscv.md patterns.
	* config/riscv/constraints.md: Implement constraints
	  cv_bi_s5 - signed 5-bit immediate.
	* config/riscv/predicates.md: Implement predicate
	  const_int5s_operand - signed 5 bit immediate.
	* doc/sourcebuild.texi: Add XCVbi documentation.

gcc/testsuite/ChangeLog:
	* gcc.target/riscv/cv-bi-beqimm-compile-1.c: New test.
	* gcc.target/riscv/cv-bi-beqimm-compile-2.c: New test.
	* gcc.target/riscv/cv-bi-bneimm-compile-1.c: New test.
	* gcc.target/riscv/cv-bi-bneimm-compile-2.c: New test.
	* lib/target-supports.exp: Add proc for XCVbi.
---
 gcc/common/config/riscv/riscv-common.cc       |  2 +
 gcc/config/riscv/constraints.md               |  6 +++
 gcc/config/riscv/corev.md                     | 14 ++++++
 gcc/config/riscv/predicates.md                |  4 ++
 gcc/config/riscv/riscv.md                     | 11 ++++-
 gcc/config/riscv/riscv.opt                    |  2 +
 gcc/doc/sourcebuild.texi                      |  3 ++
 .../gcc.target/riscv/cv-bi-beqimm-compile-1.c | 17 +++++++
 .../gcc.target/riscv/cv-bi-beqimm-compile-2.c | 48 +++++++++++++++++++
 .../gcc.target/riscv/cv-bi-bneimm-compile-1.c | 17 +++++++
 .../gcc.target/riscv/cv-bi-bneimm-compile-2.c | 48 +++++++++++++++++++
 gcc/testsuite/lib/target-supports.exp         | 13 +++++
 12 files changed, 184 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c

Comments

Kito Cheng Nov. 13, 2023, 2:41 p.m. UTC | #1 
I would prefer you suppress those patterns in riscv.cc rather than
adjust the including order, T-Head extension goes that way too, so I
would prefer to keep it using a consistent way.

you can search !TARGET_XTHEAD in riscv.md


On Mon, Nov 13, 2023 at 9:36 PM Mary Bennett <mary.bennett@embecosm.com> wrote:
>
> Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md
>
> Contributors:
>   Mary Bennett <mary.bennett@embecosm.com>
>   Nandni Jamnadas <nandni.jamnadas@embecosm.com>
>   Pietra Ferreira <pietra.ferreira@embecosm.com>
>   Charlie Keaney
>   Jessica Mills
>   Craig Blackmore <craig.blackmore@embecosm.com>
>   Simon Cook <simon.cook@embecosm.com>
>   Jeremy Bennett <jeremy.bennett@embecosm.com>
>   Helene Chelin <helene.chelin@embecosm.com>
>
> gcc/ChangeLog:
>         * common/config/riscv/riscv-common.cc: Create XCVbi extension
>           support.
>         * config/riscv/riscv.opt: Likewise.
>         * config/riscv/corev.md: Implement cv_branch<mode> pattern
>           for cv.beqimm and cv.bneimm.
>         * config/riscv/riscv.md: Change pattern priority so corev.md
>           patterns run before riscv.md patterns.
>         * config/riscv/constraints.md: Implement constraints
>           cv_bi_s5 - signed 5-bit immediate.
>         * config/riscv/predicates.md: Implement predicate
>           const_int5s_operand - signed 5 bit immediate.
>         * doc/sourcebuild.texi: Add XCVbi documentation.
>
> gcc/testsuite/ChangeLog:
>         * gcc.target/riscv/cv-bi-beqimm-compile-1.c: New test.
>         * gcc.target/riscv/cv-bi-beqimm-compile-2.c: New test.
>         * gcc.target/riscv/cv-bi-bneimm-compile-1.c: New test.
>         * gcc.target/riscv/cv-bi-bneimm-compile-2.c: New test.
>         * lib/target-supports.exp: Add proc for XCVbi.
> ---
>  gcc/common/config/riscv/riscv-common.cc       |  2 +
>  gcc/config/riscv/constraints.md               |  6 +++
>  gcc/config/riscv/corev.md                     | 14 ++++++
>  gcc/config/riscv/predicates.md                |  4 ++
>  gcc/config/riscv/riscv.md                     | 11 ++++-
>  gcc/config/riscv/riscv.opt                    |  2 +
>  gcc/doc/sourcebuild.texi                      |  3 ++
>  .../gcc.target/riscv/cv-bi-beqimm-compile-1.c | 17 +++++++
>  .../gcc.target/riscv/cv-bi-beqimm-compile-2.c | 48 +++++++++++++++++++
>  .../gcc.target/riscv/cv-bi-bneimm-compile-1.c | 17 +++++++
>  .../gcc.target/riscv/cv-bi-bneimm-compile-2.c | 48 +++++++++++++++++++
>  gcc/testsuite/lib/target-supports.exp         | 13 +++++
>  12 files changed, 184 insertions(+), 1 deletion(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
> index 6a1978bd0e4..04631e007f0 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -313,6 +313,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
>    {"xcvmac", ISA_SPEC_CLASS_NONE, 1, 0},
>    {"xcvalu", ISA_SPEC_CLASS_NONE, 1, 0},
>    {"xcvelw", ISA_SPEC_CLASS_NONE, 1, 0},
> +  {"xcvbi", ISA_SPEC_CLASS_NONE, 1, 0},
>
>    {"xtheadba", ISA_SPEC_CLASS_NONE, 1, 0},
>    {"xtheadbb", ISA_SPEC_CLASS_NONE, 1, 0},
> @@ -1669,6 +1670,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
>    {"xcvmac",        &gcc_options::x_riscv_xcv_subext, MASK_XCVMAC},
>    {"xcvalu",        &gcc_options::x_riscv_xcv_subext, MASK_XCVALU},
>    {"xcvelw",        &gcc_options::x_riscv_xcv_subext, MASK_XCVELW},
> +  {"xcvbi",         &gcc_options::x_riscv_xcv_subext, MASK_XCVBI},
>
>    {"xtheadba",      &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBA},
>    {"xtheadbb",      &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBB},
> diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
> index 2711efe68c5..718b4bd77df 100644
> --- a/gcc/config/riscv/constraints.md
> +++ b/gcc/config/riscv/constraints.md
> @@ -247,3 +247,9 @@
>    (and (match_code "const_int")
>         (and (match_test "IN_RANGE (ival, 0, 1073741823)")
>              (match_test "exact_log2 (ival + 1) != -1"))))
> +
> +(define_constraint "CV_bi_sign5"
> +  "@internal
> +   A 5-bit signed immediate for CORE-V Immediate Branch."
> +  (and (match_code "const_int")
> +       (match_test "IN_RANGE (ival, -16, 15)")))
> diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md
> index 92bf0b5d6a6..f6a1f916d7e 100644
> --- a/gcc/config/riscv/corev.md
> +++ b/gcc/config/riscv/corev.md
> @@ -706,3 +706,17 @@
>
>    [(set_attr "type" "load")
>    (set_attr "mode" "SI")])
> +
> +;; XCVBI Builtins
> +(define_insn "cv_branch<mode>"
> +  [(set (pc)
> +       (if_then_else
> +        (match_operator 1 "equality_operator"
> +                        [(match_operand:X 2 "register_operand" "r")
> +                         (match_operand:X 3 "const_int5s_operand" "CV_bi_sign5")])
> +        (label_ref (match_operand 0 "" ""))
> +        (pc)))]
> +  "TARGET_XCVBI"
> +  "cv.b%C1imm\t%2,%3,%0"
> +  [(set_attr "type" "branch")
> +   (set_attr "mode" "none")])
> diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
> index a37d035fa61..69a6319c2c8 100644
> --- a/gcc/config/riscv/predicates.md
> +++ b/gcc/config/riscv/predicates.md
> @@ -400,6 +400,10 @@
>    (ior (match_operand 0 "register_operand")
>         (match_code "const_int")))
>
> +(define_predicate "const_int5s_operand"
> +  (and (match_code "const_int")
> +       (match_test "IN_RANGE (INTVAL (op), -16, 15)")))
> +
>  ;; Predicates for the V extension.
>  (define_special_predicate "vector_length_operand"
>    (ior (match_operand 0 "pmode_register_operand")
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index ae2217d0907..9a8572e6ef3 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -579,6 +579,16 @@
>  (define_asm_attributes
>    [(set_attr "type" "multi")])
>
> +;; ..............................
> +;;
> +;;     Machine Description Patterns
> +;;
> +;; ..............................
> +
> +;; To encourage the use of CORE-V specific branch instructions, the CORE-V
> +;; instructions must be defined before the generic RISC-V instructions.
> +(include "corev.md")
> +
>  ;; Ghost instructions produce no real code and introduce no hazards.
>  ;; They exist purely to express an effect on dataflow.
>  (define_insn_reservation "ghost" 0
> @@ -3632,4 +3642,3 @@
>  (include "vector.md")
>  (include "zicond.md")
>  (include "zc.md")
> -(include "corev.md")
> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
> index 0eac6d44fae..d06c0f8f416 100644
> --- a/gcc/config/riscv/riscv.opt
> +++ b/gcc/config/riscv/riscv.opt
> @@ -413,6 +413,8 @@ Mask(XCVALU) Var(riscv_xcv_subext)
>
>  Mask(XCVELW) Var(riscv_xcv_subext)
>
> +Mask(XCVBI) Var(riscv_xcv_subext)
> +
>  TargetVariable
>  int riscv_xthead_subext
>
> diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
> index 06a6d1776ff..6fee1144238 100644
> --- a/gcc/doc/sourcebuild.texi
> +++ b/gcc/doc/sourcebuild.texi
> @@ -2484,6 +2484,9 @@ Test system has support for the CORE-V ALU extension.
>  @item cv_elw
>  Test system has support for the CORE-V ELW extension.
>
> +@item cv_bi
> +Test system has support for the CORE-V BI extension.
> +
>  @end table
>
>  @subsubsection Other hardware attributes
> diff --git a/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
> new file mode 100644
> index 00000000000..5b6ba5b8ae6
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
> @@ -0,0 +1,17 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target cv_bi } */
> +/* { dg-options "-march=rv32i_xcvbi -mabi=ilp32" } */
> +/* { dg-skip-if "" { *-*-* }  { "-O0" } { "" } } */
> +
> +/* __builtin_expect is used to provide the compiler with
> +   branch prediction information and to direct the compiler
> +   to the expected flow through the code.  */
> +
> +int
> +foo1 (int a, int x, int y)
> +{
> +    a = __builtin_expect (a, 12);
> +    return a != 10 ? x : y;
> +}
> +
> +/* { dg-final { scan-assembler-times "cv\\.beqimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),10,\(\?\:.L\[0-9\]\)" 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c b/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
> new file mode 100644
> index 00000000000..bb2e5843957
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
> @@ -0,0 +1,48 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target cv_bi } */
> +/* { dg-options "-march=rv32i_xcvbi -mabi=ilp32" } */
> +/* { dg-skip-if "" { *-*-* }  { "-O0" } { "" } } */
> +
> +/* __builtin_expect is used to provide the compiler with
> +   branch prediction information and to direct the compiler
> +   to the expected flow through the code.  */
> +
> +int
> +foo1 (int a, int x, int y)
> +{
> +    a = __builtin_expect (a, 10);
> +    return a != -16 ? x : y;
> +}
> +
> +int
> +foo2 (int a, int x, int y)
> +{
> +    a = __builtin_expect (a, 10);
> +    return a != 0 ? x : y;
> +}
> +
> +int
> +foo3 (int a, int x, int y)
> +{
> +    a = __builtin_expect (a, 10);
> +    return a != 15 ? x : y;
> +}
> +
> +int
> +foo4 (int a, int x, int y)
> +{
> +    a = __builtin_expect (a, 10);
> +    return a != -17 ? x : y;
> +}
> +
> +int
> +foo5 (int a, int x, int y)
> +{
> +    a = __builtin_expect (a, 10);
> +    return a != 16 ? x : y;
> +}
> +
> +/* { dg-final { scan-assembler-times "cv\\.beqimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),-16,\(\?\:.L\[0-9\]\)" 1 } } */
> +/* { dg-final { scan-assembler-times "cv\\.beqimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),0,\(\?\:.L\[0-9\]\)" 1 } } */
> +/* { dg-final { scan-assembler-times "cv\\.beqimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),15,\(\?\:.L\[0-9\]\)" 1 } } */
> +/* { dg-final { scan-assembler-times "beq\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),\(\?\:.L\[0-9\]+\)" 2 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
> new file mode 100644
> index 00000000000..21eab38a08d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
> @@ -0,0 +1,17 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target cv_bi } */
> +/* { dg-options "-march=rv32i_xcvbi -mabi=ilp32" } */
> +/* { dg-skip-if "" { *-*-* }  { "-O0" } { "" } } */
> +
> +/* __builtin_expect is used to provide the compiler with
> +   branch prediction information and to direct the compiler
> +   to the expected flow through the code.  */
> +
> +int
> +foo1(int a, int x, int y)
> +{
> +    a = __builtin_expect(a, 10);
> +    return a == 10 ? x : y;
> +}
> +
> +/* { dg-final { scan-assembler-times "cv\\.bneimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),10,\(\?\:.L\[0-9\]\)" 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c b/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c
> new file mode 100644
> index 00000000000..a028f684489
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c
> @@ -0,0 +1,48 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target cv_bi } */
> +/* { dg-options "-march=rv32i_xcvbi -mabi=ilp32" } */
> +/* { dg-skip-if "" { *-*-* }  { "-O0" } { "" } } */
> +
> +/* __builtin_expect is used to provide the compiler with
> +   branch prediction information and to direct the compiler
> +   to the expected flow through the code.  */
> +
> +int
> +foo1(int a, int x, int y)
> +{
> +    a = __builtin_expect(a, -16);
> +    return a == -16 ? x : y;
> +}
> +
> +int
> +foo2(int a, int x, int y)
> +{
> +    a = __builtin_expect(a, 0);
> +    return a == 0 ? x : y;
> +}
> +
> +int
> +foo3(int a, int x, int y)
> +{
> +    a = __builtin_expect(a, 15);
> +    return a == 15 ? x : y;
> +}
> +
> +int
> +foo4(int a, int x, int y)
> +{
> +    a = __builtin_expect(a, -17);
> +    return a == -17 ? x : y;
> +}
> +
> +int
> +foo5(int a, int x, int y)
> +{
> +    a = __builtin_expect(a, 16);
> +    return a == 16 ? x : y;
> +}
> +
> +/* { dg-final { scan-assembler-times "cv\\.bneimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),-16,\(\?\:.L\[0-9\]\)" 1 } } */
> +/* { dg-final { scan-assembler-times "cv\\.bneimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),0,\(\?\:.L\[0-9\]\)" 1 } } */
> +/* { dg-final { scan-assembler-times "cv\\.bneimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),15,\(\?\:.L\[0-9\]\)" 1 } } */
> +/* { dg-final { scan-assembler-times "bne\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),\(\?\:.L\[0-9\]+\)" 2 } } */
> diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
> index f388360ae56..0eae746e848 100644
> --- a/gcc/testsuite/lib/target-supports.exp
> +++ b/gcc/testsuite/lib/target-supports.exp
> @@ -13098,6 +13098,19 @@ proc check_effective_target_cv_elw { } {
>      } "-march=rv32i_xcvelw" ]
>  }
>
> +# Return 1 if the CORE-V BI extension is available
> +proc check_effective_target_cv_bi { } {
> +    if { !([istarget riscv*-*-*]) } {
> +         return 0
> +     }
> +    return [check_no_compiler_messages cv_bi object {
> +        void foo (void)
> +        {
> +          asm ("cv.beqimm t0, -16, foo");
> +        }
> +    } "-march=rv32i_xcvbi" ]
> +}
> +
>  proc check_effective_target_loongarch_sx { } {
>      return [check_no_compiler_messages loongarch_lsx assembly {
>         #if !defined(__loongarch_sx)
> --
> 2.34.1
>
Patrick O'Neill Nov. 13, 2023, 7:14 p.m. UTC | #2 
Hi Mary,

GCC tip-of-tree with this patch series applied fails to build glibc with:
--with-arch=rv32imac --with-abi=ilp32
--with-arch=rv32imafdc --with-abi=ilp32d

Failing command:
./bin/riscv32-unknown-elf-gcc 
-B/scratch/tc-testing/tc-nov-13-zcvbi-series/build/build-newlib/riscv32-unknown-elf/newlib/ 
-isystem 
/scratch/tc-testing/tc-nov-13-zcvbi-series/build/build-newlib/riscv32-unknown-elf/newlib/targ-include 
-isystem 
/scratch/tc-testing/tc-nov-13-zcvbi-series/newlib/newlib/libc/include 
-B/scratch/tc-testing/tc-nov-13-zcvbi-series/build/build-newlib/riscv32-unknown-elf/libgloss/riscv32 
-L/scratch/tc-testing/tc-nov-13-zcvbi-series/build/build-newlib/riscv32-unknown-elf/libgloss/libnosys 
-L/scratch/tc-testing/tc-nov-13-zcvbi-series/newlib/libgloss/riscv32 
-DPACKAGE_NAME=\"newlib\" -DPACKAGE_TARNAME=\"newlib\" 
-DPACKAGE_VERSION=\"4.1.0\" -DPACKAGE_STRING=\"newlib\ 4.1.0\" 
-DPACKAGE_BUGREPORT=\"\" -DPACKAGE_URL=\"\" -I. 
-I/scratch/tc-testing/tc-nov-13-zcvbi-series/build/../newlib/newlib/libc/time 
-fno-builtin -DHAVE_NANOSLEEP      -O2 -D_POSIX_MODE -ffunction-sections 
-fdata-sections    -mcmodel=medlow -c -o lib_a-mktime.o `test -f 
'mktime.c' || echo 
'/scratch/tc-testing/tc-nov-13-zcvbi-series/build/../newlib/newlib/libc/time/'`mktime.c
during RTL pass: combine
/scratch/tc-testing/tc-nov-13-zcvbi-series/build/../newlib/newlib/libc/time/mktime.c: 
In function 'validate_structure':
/scratch/tc-testing/tc-nov-13-zcvbi-series/build/../newlib/newlib/libc/time/mktime.c:148:1: 
internal compiler error: Segmentation fault
   148 | }
       | ^
0x1276843 crash_signal
         ../../../gcc/gcc/toplev.cc:316
0x2136c93 recog_1349
         ../../../gcc/gcc/config/riscv/thead.md:438
0x21dcab5 recog_for_combine_1
         ../../../gcc/gcc/combine.cc:11382
0x21e12ae recog_for_combine
         ../../../gcc/gcc/combine.cc:11652
0x21f594a try_combine
         ../../../gcc/gcc/combine.cc:3867
0x21f8159 combine_instructions
         ../../../gcc/gcc/combine.cc:1285
0x21f8159 rest_of_handle_combine
         ../../../gcc/gcc/combine.cc:15080
0x21f8159 execute
         ../../../gcc/gcc/combine.cc:15124
Please submit a full bug report, with preprocessed source (by using 
-freport-bug).
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.

Creduced testcase:
./bin/riscv32-unknown-elf-gcc -O1 mktime.c -freport-bug
int a, b;
void c() { a = b % 7; }

during RTL pass: combine
mktime.c: In function 'c':
mktime.c:2:23: internal compiler error: Segmentation fault
     2 | void c() { a = b % 7; }
       |                       ^
0x1276843 crash_signal
         ../../../gcc/gcc/toplev.cc:316
0x2136c93 recog_1349
         ../../../gcc/gcc/config/riscv/thead.md:438
0x21dcab5 recog_for_combine_1
         ../../../gcc/gcc/combine.cc:11382
0x21e12ae recog_for_combine
         ../../../gcc/gcc/combine.cc:11652
0x21f594a try_combine
         ../../../gcc/gcc/combine.cc:3867
0x21f8159 combine_instructions
         ../../../gcc/gcc/combine.cc:1285
0x21f8159 rest_of_handle_combine
         ../../../gcc/gcc/combine.cc:15080
0x21f8159 execute
         ../../../gcc/gcc/combine.cc:15124
Please submit a full bug report, with preprocessed source.
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.
Preprocessed source stored into /tmp/ccJL816S.out file, please attach 
this to your bugreport.

I've attached the -freport-bug output to this email.

Thanks,
Patrick

glibc: a704fd9a133bfb10510e18702f48a6a9c88dbbd5
gcc base hash: 2020bce38cf2e02cbd1097faa8f1fd6586364a7e

On 11/13/23 05:35, Mary Bennett wrote:
> Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md
>
> Contributors:
>    Mary Bennett <mary.bennett@embecosm.com>
>    Nandni Jamnadas <nandni.jamnadas@embecosm.com>
>    Pietra Ferreira <pietra.ferreira@embecosm.com>
>    Charlie Keaney
>    Jessica Mills
>    Craig Blackmore <craig.blackmore@embecosm.com>
>    Simon Cook <simon.cook@embecosm.com>
>    Jeremy Bennett <jeremy.bennett@embecosm.com>
>    Helene Chelin <helene.chelin@embecosm.com>
>
> gcc/ChangeLog:
> 	* common/config/riscv/riscv-common.cc: Create XCVbi extension
> 	  support.
> 	* config/riscv/riscv.opt: Likewise.
> 	* config/riscv/corev.md: Implement cv_branch<mode> pattern
> 	  for cv.beqimm and cv.bneimm.
> 	* config/riscv/riscv.md: Change pattern priority so corev.md
> 	  patterns run before riscv.md patterns.
> 	* config/riscv/constraints.md: Implement constraints
> 	  cv_bi_s5 - signed 5-bit immediate.
> 	* config/riscv/predicates.md: Implement predicate
> 	  const_int5s_operand - signed 5 bit immediate.
> 	* doc/sourcebuild.texi: Add XCVbi documentation.
>
> gcc/testsuite/ChangeLog:
> 	* gcc.target/riscv/cv-bi-beqimm-compile-1.c: New test.
> 	* gcc.target/riscv/cv-bi-beqimm-compile-2.c: New test.
> 	* gcc.target/riscv/cv-bi-bneimm-compile-1.c: New test.
> 	* gcc.target/riscv/cv-bi-bneimm-compile-2.c: New test.
> 	* lib/target-supports.exp: Add proc for XCVbi.
> ---
>   gcc/common/config/riscv/riscv-common.cc       |  2 +
>   gcc/config/riscv/constraints.md               |  6 +++
>   gcc/config/riscv/corev.md                     | 14 ++++++
>   gcc/config/riscv/predicates.md                |  4 ++
>   gcc/config/riscv/riscv.md                     | 11 ++++-
>   gcc/config/riscv/riscv.opt                    |  2 +
>   gcc/doc/sourcebuild.texi                      |  3 ++
>   .../gcc.target/riscv/cv-bi-beqimm-compile-1.c | 17 +++++++
>   .../gcc.target/riscv/cv-bi-beqimm-compile-2.c | 48 +++++++++++++++++++
>   .../gcc.target/riscv/cv-bi-bneimm-compile-1.c | 17 +++++++
>   .../gcc.target/riscv/cv-bi-bneimm-compile-2.c | 48 +++++++++++++++++++
>   gcc/testsuite/lib/target-supports.exp         | 13 +++++
>   12 files changed, 184 insertions(+), 1 deletion(-)
>   create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
>   create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
>   create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
>   create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
> index 6a1978bd0e4..04631e007f0 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -313,6 +313,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
>     {"xcvmac", ISA_SPEC_CLASS_NONE, 1, 0},
>     {"xcvalu", ISA_SPEC_CLASS_NONE, 1, 0},
>     {"xcvelw", ISA_SPEC_CLASS_NONE, 1, 0},
> +  {"xcvbi", ISA_SPEC_CLASS_NONE, 1, 0},
>   
>     {"xtheadba", ISA_SPEC_CLASS_NONE, 1, 0},
>     {"xtheadbb", ISA_SPEC_CLASS_NONE, 1, 0},
> @@ -1669,6 +1670,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
>     {"xcvmac",        &gcc_options::x_riscv_xcv_subext, MASK_XCVMAC},
>     {"xcvalu",        &gcc_options::x_riscv_xcv_subext, MASK_XCVALU},
>     {"xcvelw",        &gcc_options::x_riscv_xcv_subext, MASK_XCVELW},
> +  {"xcvbi",         &gcc_options::x_riscv_xcv_subext, MASK_XCVBI},
>   
>     {"xtheadba",      &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBA},
>     {"xtheadbb",      &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBB},
> diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
> index 2711efe68c5..718b4bd77df 100644
> --- a/gcc/config/riscv/constraints.md
> +++ b/gcc/config/riscv/constraints.md
> @@ -247,3 +247,9 @@
>     (and (match_code "const_int")
>          (and (match_test "IN_RANGE (ival, 0, 1073741823)")
>               (match_test "exact_log2 (ival + 1) != -1"))))
> +
> +(define_constraint "CV_bi_sign5"
> +  "@internal
> +   A 5-bit signed immediate for CORE-V Immediate Branch."
> +  (and (match_code "const_int")
> +       (match_test "IN_RANGE (ival, -16, 15)")))
> diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md
> index 92bf0b5d6a6..f6a1f916d7e 100644
> --- a/gcc/config/riscv/corev.md
> +++ b/gcc/config/riscv/corev.md
> @@ -706,3 +706,17 @@
>   
>     [(set_attr "type" "load")
>     (set_attr "mode" "SI")])
> +
> +;; XCVBI Builtins
> +(define_insn "cv_branch<mode>"
> +  [(set (pc)
> +	(if_then_else
> +	 (match_operator 1 "equality_operator"
> +			 [(match_operand:X 2 "register_operand" "r")
> +			  (match_operand:X 3 "const_int5s_operand" "CV_bi_sign5")])
> +	 (label_ref (match_operand 0 "" ""))
> +	 (pc)))]
> +  "TARGET_XCVBI"
> +  "cv.b%C1imm\t%2,%3,%0"
> +  [(set_attr "type" "branch")
> +   (set_attr "mode" "none")])
> diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
> index a37d035fa61..69a6319c2c8 100644
> --- a/gcc/config/riscv/predicates.md
> +++ b/gcc/config/riscv/predicates.md
> @@ -400,6 +400,10 @@
>     (ior (match_operand 0 "register_operand")
>          (match_code "const_int")))
>   
> +(define_predicate "const_int5s_operand"
> +  (and (match_code "const_int")
> +       (match_test "IN_RANGE (INTVAL (op), -16, 15)")))
> +
>   ;; Predicates for the V extension.
>   (define_special_predicate "vector_length_operand"
>     (ior (match_operand 0 "pmode_register_operand")
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index ae2217d0907..9a8572e6ef3 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -579,6 +579,16 @@
>   (define_asm_attributes
>     [(set_attr "type" "multi")])
>   
> +;; ..............................
> +;;
> +;;	Machine Description Patterns
> +;;
> +;; ..............................
> +
> +;; To encourage the use of CORE-V specific branch instructions, the CORE-V
> +;; instructions must be defined before the generic RISC-V instructions.
> +(include "corev.md")
> +
>   ;; Ghost instructions produce no real code and introduce no hazards.
>   ;; They exist purely to express an effect on dataflow.
>   (define_insn_reservation "ghost" 0
> @@ -3632,4 +3642,3 @@
>   (include "vector.md")
>   (include "zicond.md")
>   (include "zc.md")
> -(include "corev.md")
> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
> index 0eac6d44fae..d06c0f8f416 100644
> --- a/gcc/config/riscv/riscv.opt
> +++ b/gcc/config/riscv/riscv.opt
> @@ -413,6 +413,8 @@ Mask(XCVALU) Var(riscv_xcv_subext)
>   
>   Mask(XCVELW) Var(riscv_xcv_subext)
>   
> +Mask(XCVBI) Var(riscv_xcv_subext)
> +
>   TargetVariable
>   int riscv_xthead_subext
>   
> diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
> index 06a6d1776ff..6fee1144238 100644
> --- a/gcc/doc/sourcebuild.texi
> +++ b/gcc/doc/sourcebuild.texi
> @@ -2484,6 +2484,9 @@ Test system has support for the CORE-V ALU extension.
>   @item cv_elw
>   Test system has support for the CORE-V ELW extension.
>   
> +@item cv_bi
> +Test system has support for the CORE-V BI extension.
> +
>   @end table
>   
>   @subsubsection Other hardware attributes
> diff --git a/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
> new file mode 100644
> index 00000000000..5b6ba5b8ae6
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
> @@ -0,0 +1,17 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target cv_bi } */
> +/* { dg-options "-march=rv32i_xcvbi -mabi=ilp32" } */
> +/* { dg-skip-if "" { *-*-* }  { "-O0" } { "" } } */
> +
> +/* __builtin_expect is used to provide the compiler with
> +   branch prediction information and to direct the compiler
> +   to the expected flow through the code.  */
> +
> +int
> +foo1 (int a, int x, int y)
> +{
> +    a = __builtin_expect (a, 12);
> +    return a != 10 ? x : y;
> +}
> +
> +/* { dg-final { scan-assembler-times "cv\\.beqimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),10,\(\?\:.L\[0-9\]\)" 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c b/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
> new file mode 100644
> index 00000000000..bb2e5843957
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
> @@ -0,0 +1,48 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target cv_bi } */
> +/* { dg-options "-march=rv32i_xcvbi -mabi=ilp32" } */
> +/* { dg-skip-if "" { *-*-* }  { "-O0" } { "" } } */
> +
> +/* __builtin_expect is used to provide the compiler with
> +   branch prediction information and to direct the compiler
> +   to the expected flow through the code.  */
> +
> +int
> +foo1 (int a, int x, int y)
> +{
> +    a = __builtin_expect (a, 10);
> +    return a != -16 ? x : y;
> +}
> +
> +int
> +foo2 (int a, int x, int y)
> +{
> +    a = __builtin_expect (a, 10);
> +    return a != 0 ? x : y;
> +}
> +
> +int
> +foo3 (int a, int x, int y)
> +{
> +    a = __builtin_expect (a, 10);
> +    return a != 15 ? x : y;
> +}
> +
> +int
> +foo4 (int a, int x, int y)
> +{
> +    a = __builtin_expect (a, 10);
> +    return a != -17 ? x : y;
> +}
> +
> +int
> +foo5 (int a, int x, int y)
> +{
> +    a = __builtin_expect (a, 10);
> +    return a != 16 ? x : y;
> +}
> +
> +/* { dg-final { scan-assembler-times "cv\\.beqimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),-16,\(\?\:.L\[0-9\]\)" 1 } } */
> +/* { dg-final { scan-assembler-times "cv\\.beqimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),0,\(\?\:.L\[0-9\]\)" 1 } } */
> +/* { dg-final { scan-assembler-times "cv\\.beqimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),15,\(\?\:.L\[0-9\]\)" 1 } } */
> +/* { dg-final { scan-assembler-times "beq\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),\(\?\:.L\[0-9\]+\)" 2 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
> new file mode 100644
> index 00000000000..21eab38a08d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
> @@ -0,0 +1,17 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target cv_bi } */
> +/* { dg-options "-march=rv32i_xcvbi -mabi=ilp32" } */
> +/* { dg-skip-if "" { *-*-* }  { "-O0" } { "" } } */
> +
> +/* __builtin_expect is used to provide the compiler with
> +   branch prediction information and to direct the compiler
> +   to the expected flow through the code.  */
> +
> +int
> +foo1(int a, int x, int y)
> +{
> +    a = __builtin_expect(a, 10);
> +    return a == 10 ? x : y;
> +}
> +
> +/* { dg-final { scan-assembler-times "cv\\.bneimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),10,\(\?\:.L\[0-9\]\)" 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c b/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c
> new file mode 100644
> index 00000000000..a028f684489
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c
> @@ -0,0 +1,48 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target cv_bi } */
> +/* { dg-options "-march=rv32i_xcvbi -mabi=ilp32" } */
> +/* { dg-skip-if "" { *-*-* }  { "-O0" } { "" } } */
> +
> +/* __builtin_expect is used to provide the compiler with
> +   branch prediction information and to direct the compiler
> +   to the expected flow through the code.  */
> +
> +int
> +foo1(int a, int x, int y)
> +{
> +    a = __builtin_expect(a, -16);
> +    return a == -16 ? x : y;
> +}
> +
> +int
> +foo2(int a, int x, int y)
> +{
> +    a = __builtin_expect(a, 0);
> +    return a == 0 ? x : y;
> +}
> +
> +int
> +foo3(int a, int x, int y)
> +{
> +    a = __builtin_expect(a, 15);
> +    return a == 15 ? x : y;
> +}
> +
> +int
> +foo4(int a, int x, int y)
> +{
> +    a = __builtin_expect(a, -17);
> +    return a == -17 ? x : y;
> +}
> +
> +int
> +foo5(int a, int x, int y)
> +{
> +    a = __builtin_expect(a, 16);
> +    return a == 16 ? x : y;
> +}
> +
> +/* { dg-final { scan-assembler-times "cv\\.bneimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),-16,\(\?\:.L\[0-9\]\)" 1 } } */
> +/* { dg-final { scan-assembler-times "cv\\.bneimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),0,\(\?\:.L\[0-9\]\)" 1 } } */
> +/* { dg-final { scan-assembler-times "cv\\.bneimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),15,\(\?\:.L\[0-9\]\)" 1 } } */
> +/* { dg-final { scan-assembler-times "bne\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),\(\?\:.L\[0-9\]+\)" 2 } } */
> diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
> index f388360ae56..0eae746e848 100644
> --- a/gcc/testsuite/lib/target-supports.exp
> +++ b/gcc/testsuite/lib/target-supports.exp
> @@ -13098,6 +13098,19 @@ proc check_effective_target_cv_elw { } {
>       } "-march=rv32i_xcvelw" ]
>   }
>   
> +# Return 1 if the CORE-V BI extension is available
> +proc check_effective_target_cv_bi { } {
> +    if { !([istarget riscv*-*-*]) } {
> +         return 0
> +     }
> +    return [check_no_compiler_messages cv_bi object {
> +        void foo (void)
> +        {
> +          asm ("cv.beqimm t0, -16, foo");
> +        }
> +    } "-march=rv32i_xcvbi" ]
> +}
> +
>   proc check_effective_target_loongarch_sx { } {
>       return [check_no_compiler_messages loongarch_lsx assembly {
>          #if !defined(__loongarch_sx)
// Target: riscv32-unknown-elf
// Configured with: /scratch/tc-testing/tc-nov-13-zcvbi-series/build/../gcc/configure --target=riscv32-unknown-elf --prefix=/scratch/tc-testing/tc-nov-13-zcvbi-series/build --disable-shared --disable-threads --disable-tls --enable-languages=c,c++ --with-system-zlib --with-newlib --with-sysroot=/scratch/tc-testing/tc-nov-13-zcvbi-series/build/riscv32-unknown-elf --disable-libmudflap --disable-libssp --disable-libquadmath --disable-libgomp --disable-nls --disable-tm-clone-registry --src=../../gcc --disable-multilib --with-abi=ilp32 --with-arch=rv32imac --with-tune=rocket --with-isa-spec=20191213 'CFLAGS_FOR_TARGET=-Os    -mcmodel=medlow' 'CXXFLAGS_FOR_TARGET=-Os    -mcmodel=medlow'
// Thread model: single
// Supported LTO compression algorithms: zlib zstd
// gcc version 14.0.0 20231109 (experimental) (GCC) 
// 
// during RTL pass: combine
// mktime.c: In function 'c':
// mktime.c:2:23: internal compiler error: Segmentation fault
//     2 | void c() { a = b % 7; }
//       |                       ^
// 0x1276843 crash_signal
// 	../../../gcc/gcc/toplev.cc:316
// 0x2136c93 recog_1349
// 	../../../gcc/gcc/config/riscv/thead.md:438
// 0x21dcab5 recog_for_combine_1
// 	../../../gcc/gcc/combine.cc:11382
// 0x21e12ae recog_for_combine
// 	../../../gcc/gcc/combine.cc:11652
// 0x21f594a try_combine
// 	../../../gcc/gcc/combine.cc:3867
// 0x21f8159 combine_instructions
// 	../../../gcc/gcc/combine.cc:1285
// 0x21f8159 rest_of_handle_combine
// 	../../../gcc/gcc/combine.cc:15080
// 0x21f8159 execute
// 	../../../gcc/gcc/combine.cc:15124
// Please submit a full bug report, with preprocessed source.
// Please include the complete backtrace with any bug report.
// See <https://gcc.gnu.org/bugs/> for instructions.

// /scratch/tc-testing/tc-nov-13-zcvbi-series/build/libexec/gcc/riscv32-unknown-elf/14.0.0/cc1 -quiet -imultilib . mktime.c -quiet -dumpdir a- -dumpbase mktime.c -dumpbase-ext .c -mtune=rocket -march=rv32imac -mabi=ilp32 -misa-spec=20191213 -march=rv32imac -O1 -freport-bug -o - -frandom-seed=0 -fdump-noaddr

# 0 "mktime.c"
# 0 "<built-in>"
# 0 "<command-line>"
# 1 "mktime.c"
int a, b;
void c() { a = b % 7; }
diff mbox series

Patch

diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index 6a1978bd0e4..04631e007f0 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -313,6 +313,7 @@  static const struct riscv_ext_version riscv_ext_version_table[] =
   {"xcvmac", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xcvalu", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xcvelw", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"xcvbi", ISA_SPEC_CLASS_NONE, 1, 0},
 
   {"xtheadba", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xtheadbb", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1669,6 +1670,7 @@  static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
   {"xcvmac",        &gcc_options::x_riscv_xcv_subext, MASK_XCVMAC},
   {"xcvalu",        &gcc_options::x_riscv_xcv_subext, MASK_XCVALU},
   {"xcvelw",        &gcc_options::x_riscv_xcv_subext, MASK_XCVELW},
+  {"xcvbi",         &gcc_options::x_riscv_xcv_subext, MASK_XCVBI},
 
   {"xtheadba",      &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBA},
   {"xtheadbb",      &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBB},
diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 2711efe68c5..718b4bd77df 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -247,3 +247,9 @@ 
   (and (match_code "const_int")
        (and (match_test "IN_RANGE (ival, 0, 1073741823)")
             (match_test "exact_log2 (ival + 1) != -1"))))
+
+(define_constraint "CV_bi_sign5"
+  "@internal
+   A 5-bit signed immediate for CORE-V Immediate Branch."
+  (and (match_code "const_int")
+       (match_test "IN_RANGE (ival, -16, 15)")))
diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md
index 92bf0b5d6a6..f6a1f916d7e 100644
--- a/gcc/config/riscv/corev.md
+++ b/gcc/config/riscv/corev.md
@@ -706,3 +706,17 @@ 
 
   [(set_attr "type" "load")
   (set_attr "mode" "SI")])
+
+;; XCVBI Builtins
+(define_insn "cv_branch<mode>"
+  [(set (pc)
+	(if_then_else
+	 (match_operator 1 "equality_operator"
+			 [(match_operand:X 2 "register_operand" "r")
+			  (match_operand:X 3 "const_int5s_operand" "CV_bi_sign5")])
+	 (label_ref (match_operand 0 "" ""))
+	 (pc)))]
+  "TARGET_XCVBI"
+  "cv.b%C1imm\t%2,%3,%0"
+  [(set_attr "type" "branch")
+   (set_attr "mode" "none")])
diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index a37d035fa61..69a6319c2c8 100644
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -400,6 +400,10 @@ 
   (ior (match_operand 0 "register_operand")
        (match_code "const_int")))
 
+(define_predicate "const_int5s_operand"
+  (and (match_code "const_int")
+       (match_test "IN_RANGE (INTVAL (op), -16, 15)")))
+
 ;; Predicates for the V extension.
 (define_special_predicate "vector_length_operand"
   (ior (match_operand 0 "pmode_register_operand")
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index ae2217d0907..9a8572e6ef3 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -579,6 +579,16 @@ 
 (define_asm_attributes
   [(set_attr "type" "multi")])
 
+;; ..............................
+;;
+;;	Machine Description Patterns
+;;
+;; ..............................
+
+;; To encourage the use of CORE-V specific branch instructions, the CORE-V
+;; instructions must be defined before the generic RISC-V instructions.
+(include "corev.md")
+
 ;; Ghost instructions produce no real code and introduce no hazards.
 ;; They exist purely to express an effect on dataflow.
 (define_insn_reservation "ghost" 0
@@ -3632,4 +3642,3 @@ 
 (include "vector.md")
 (include "zicond.md")
 (include "zc.md")
-(include "corev.md")
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 0eac6d44fae..d06c0f8f416 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -413,6 +413,8 @@  Mask(XCVALU) Var(riscv_xcv_subext)
 
 Mask(XCVELW) Var(riscv_xcv_subext)
 
+Mask(XCVBI) Var(riscv_xcv_subext)
+
 TargetVariable
 int riscv_xthead_subext
 
diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index 06a6d1776ff..6fee1144238 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -2484,6 +2484,9 @@  Test system has support for the CORE-V ALU extension.
 @item cv_elw
 Test system has support for the CORE-V ELW extension.
 
+@item cv_bi
+Test system has support for the CORE-V BI extension.
+
 @end table
 
 @subsubsection Other hardware attributes
diff --git a/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
new file mode 100644
index 00000000000..5b6ba5b8ae6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
@@ -0,0 +1,17 @@ 
+/* { dg-do compile } */
+/* { dg-require-effective-target cv_bi } */
+/* { dg-options "-march=rv32i_xcvbi -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* }  { "-O0" } { "" } } */
+
+/* __builtin_expect is used to provide the compiler with
+   branch prediction information and to direct the compiler
+   to the expected flow through the code.  */
+
+int
+foo1 (int a, int x, int y)
+{
+    a = __builtin_expect (a, 12);
+    return a != 10 ? x : y;
+}
+
+/* { dg-final { scan-assembler-times "cv\\.beqimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),10,\(\?\:.L\[0-9\]\)" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c b/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
new file mode 100644
index 00000000000..bb2e5843957
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
@@ -0,0 +1,48 @@ 
+/* { dg-do compile } */
+/* { dg-require-effective-target cv_bi } */
+/* { dg-options "-march=rv32i_xcvbi -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* }  { "-O0" } { "" } } */
+
+/* __builtin_expect is used to provide the compiler with
+   branch prediction information and to direct the compiler
+   to the expected flow through the code.  */
+
+int
+foo1 (int a, int x, int y)
+{
+    a = __builtin_expect (a, 10);
+    return a != -16 ? x : y;
+}
+
+int
+foo2 (int a, int x, int y)
+{
+    a = __builtin_expect (a, 10);
+    return a != 0 ? x : y;
+}
+
+int
+foo3 (int a, int x, int y)
+{
+    a = __builtin_expect (a, 10);
+    return a != 15 ? x : y;
+}
+
+int
+foo4 (int a, int x, int y)
+{
+    a = __builtin_expect (a, 10);
+    return a != -17 ? x : y;
+}
+
+int
+foo5 (int a, int x, int y)
+{
+    a = __builtin_expect (a, 10);
+    return a != 16 ? x : y;
+}
+
+/* { dg-final { scan-assembler-times "cv\\.beqimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),-16,\(\?\:.L\[0-9\]\)" 1 } } */
+/* { dg-final { scan-assembler-times "cv\\.beqimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),0,\(\?\:.L\[0-9\]\)" 1 } } */
+/* { dg-final { scan-assembler-times "cv\\.beqimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),15,\(\?\:.L\[0-9\]\)" 1 } } */
+/* { dg-final { scan-assembler-times "beq\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),\(\?\:.L\[0-9\]+\)" 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
new file mode 100644
index 00000000000..21eab38a08d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
@@ -0,0 +1,17 @@ 
+/* { dg-do compile } */
+/* { dg-require-effective-target cv_bi } */
+/* { dg-options "-march=rv32i_xcvbi -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* }  { "-O0" } { "" } } */
+
+/* __builtin_expect is used to provide the compiler with
+   branch prediction information and to direct the compiler
+   to the expected flow through the code.  */
+
+int
+foo1(int a, int x, int y)
+{
+    a = __builtin_expect(a, 10);
+    return a == 10 ? x : y;
+}
+
+/* { dg-final { scan-assembler-times "cv\\.bneimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),10,\(\?\:.L\[0-9\]\)" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c b/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c
new file mode 100644
index 00000000000..a028f684489
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c
@@ -0,0 +1,48 @@ 
+/* { dg-do compile } */
+/* { dg-require-effective-target cv_bi } */
+/* { dg-options "-march=rv32i_xcvbi -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* }  { "-O0" } { "" } } */
+
+/* __builtin_expect is used to provide the compiler with
+   branch prediction information and to direct the compiler
+   to the expected flow through the code.  */
+
+int
+foo1(int a, int x, int y)
+{
+    a = __builtin_expect(a, -16);
+    return a == -16 ? x : y;
+}
+
+int
+foo2(int a, int x, int y)
+{
+    a = __builtin_expect(a, 0);
+    return a == 0 ? x : y;
+}
+
+int
+foo3(int a, int x, int y)
+{
+    a = __builtin_expect(a, 15);
+    return a == 15 ? x : y;
+}
+
+int
+foo4(int a, int x, int y)
+{
+    a = __builtin_expect(a, -17);
+    return a == -17 ? x : y;
+}
+
+int
+foo5(int a, int x, int y)
+{
+    a = __builtin_expect(a, 16);
+    return a == 16 ? x : y;
+}
+
+/* { dg-final { scan-assembler-times "cv\\.bneimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),-16,\(\?\:.L\[0-9\]\)" 1 } } */
+/* { dg-final { scan-assembler-times "cv\\.bneimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),0,\(\?\:.L\[0-9\]\)" 1 } } */
+/* { dg-final { scan-assembler-times "cv\\.bneimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),15,\(\?\:.L\[0-9\]\)" 1 } } */
+/* { dg-final { scan-assembler-times "bne\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),\(\?\:.L\[0-9\]+\)" 2 } } */
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index f388360ae56..0eae746e848 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -13098,6 +13098,19 @@  proc check_effective_target_cv_elw { } {
     } "-march=rv32i_xcvelw" ]
 }
 
+# Return 1 if the CORE-V BI extension is available
+proc check_effective_target_cv_bi { } {
+    if { !([istarget riscv*-*-*]) } {
+         return 0
+     }
+    return [check_no_compiler_messages cv_bi object {
+        void foo (void)
+        {
+          asm ("cv.beqimm t0, -16, foo");
+        }
+    } "-march=rv32i_xcvbi" ]
+}
+
 proc check_effective_target_loongarch_sx { } {
     return [check_no_compiler_messages loongarch_lsx assembly {
        #if !defined(__loongarch_sx)