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Mon, 13 Nov 2023 05:35:46 -0800 (PST) Received: from troughton.sou.embecosm-corp.com ([212.69.42.53]) by smtp.gmail.com with ESMTPSA id d13-20020a056000114d00b003140f47224csm5420493wrx.15.2023.11.13.05.35.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Nov 2023 05:35:45 -0800 (PST) From: Mary Bennett To: gcc-patches@gcc.gnu.org Cc: mary.bennett@embecosm.com Subject: [PATCH v2 1/3] RISC-V: Add support for XCVelw extension in CV32E40P Date: Mon, 13 Nov 2023 13:35:28 +0000 Message-Id: <20231113133530.1727444-2-mary.bennett@embecosm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231113133530.1727444-1-mary.bennett@embecosm.com> References: <20231108110914.2710021-1-mary.bennett@embecosm.com> <20231113133530.1727444-1-mary.bennett@embecosm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md Contributors: Mary Bennett Nandni Jamnadas Pietra Ferreira Charlie Keaney Jessica Mills Craig Blackmore Simon Cook Jeremy Bennett Helene Chelin gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add XCVelw. * config/riscv/corev.def: Likewise. * config/riscv/corev.md: Likewise. * config/riscv/riscv-builtins.cc (AVAIL): Likewise. * config/riscv/riscv-ftypes.def: Likewise. * config/riscv/riscv.opt: Likewise. * doc/extend.texi: Add XCVelw builtin documentation. * doc/sourcebuild.texi: Likewise. gcc/testsuite/ChangeLog: * gcc.target/riscv/cv-elw-compile-1.c: Create test for cv.elw. * testsuite/lib/target-supports.exp: Add proc for the XCVelw extension. --- gcc/common/config/riscv/riscv-common.cc | 2 ++ gcc/config/riscv/corev.def | 3 +++ gcc/config/riscv/corev.md | 15 +++++++++++++++ gcc/config/riscv/riscv-builtins.cc | 2 ++ gcc/config/riscv/riscv-ftypes.def | 1 + gcc/config/riscv/riscv.opt | 2 ++ gcc/doc/extend.texi | 8 ++++++++ gcc/doc/sourcebuild.texi | 3 +++ .../gcc.target/riscv/cv-elw-elw-compile-1.c | 11 +++++++++++ gcc/testsuite/lib/target-supports.exp | 13 +++++++++++++ 10 files changed, 60 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/cv-elw-elw-compile-1.c diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 526dbb7603b..6a1978bd0e4 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -312,6 +312,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"xcvmac", ISA_SPEC_CLASS_NONE, 1, 0}, {"xcvalu", ISA_SPEC_CLASS_NONE, 1, 0}, + {"xcvelw", ISA_SPEC_CLASS_NONE, 1, 0}, {"xtheadba", ISA_SPEC_CLASS_NONE, 1, 0}, {"xtheadbb", ISA_SPEC_CLASS_NONE, 1, 0}, @@ -1667,6 +1668,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"xcvmac", &gcc_options::x_riscv_xcv_subext, MASK_XCVMAC}, {"xcvalu", &gcc_options::x_riscv_xcv_subext, MASK_XCVALU}, + {"xcvelw", &gcc_options::x_riscv_xcv_subext, MASK_XCVELW}, {"xtheadba", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBA}, {"xtheadbb", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBB}, diff --git a/gcc/config/riscv/corev.def b/gcc/config/riscv/corev.def index 17580df3c41..3b9ec029d06 100644 --- a/gcc/config/riscv/corev.def +++ b/gcc/config/riscv/corev.def @@ -41,3 +41,6 @@ RISCV_BUILTIN (cv_alu_subN, "cv_alu_subN", RISCV_BUILTIN_DIRECT, RISCV_SI_FT RISCV_BUILTIN (cv_alu_subuN, "cv_alu_subuN", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_UQI, cvalu), RISCV_BUILTIN (cv_alu_subRN, "cv_alu_subRN", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI_UQI, cvalu), RISCV_BUILTIN (cv_alu_subuRN, "cv_alu_subuRN",RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_UQI, cvalu), + +// XCVELW +RISCV_BUILTIN (cv_elw_elw_si, "cv_elw_elw", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_VOID_PTR, cvelw), diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md index 1350bd4b81e..c7a2ba07bcc 100644 --- a/gcc/config/riscv/corev.md +++ b/gcc/config/riscv/corev.md @@ -24,6 +24,9 @@ UNSPEC_CV_ALU_CLIPR UNSPEC_CV_ALU_CLIPU UNSPEC_CV_ALU_CLIPUR + + ;;CORE-V EVENT LOAD + UNSPECV_CV_ELW ]) ;; XCVMAC extension. @@ -691,3 +694,15 @@ cv.suburnr\t%0,%2,%3" [(set_attr "type" "arith") (set_attr "mode" "SI")]) + +;; XCVELW builtins +(define_insn "riscv_cv_elw_elw_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec_volatile [(match_operand:SI 1 "move_operand" "p")] + UNSPECV_CV_ELW))] + + "TARGET_XCVELW && !TARGET_64BIT" + "cv.elw\t%0,%a1" + + [(set_attr "type" "load") + (set_attr "mode" "SI")]) diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc index fc3976f3ba1..5ee11ebe3bc 100644 --- a/gcc/config/riscv/riscv-builtins.cc +++ b/gcc/config/riscv/riscv-builtins.cc @@ -128,6 +128,7 @@ AVAIL (hint_pause, (!0)) // CORE-V AVAIL AVAIL (cvmac, TARGET_XCVMAC && !TARGET_64BIT) AVAIL (cvalu, TARGET_XCVALU && !TARGET_64BIT) +AVAIL (cvelw, TARGET_XCVELW && !TARGET_64BIT) /* Construct a riscv_builtin_description from the given arguments. @@ -168,6 +169,7 @@ AVAIL (cvalu, TARGET_XCVALU && !TARGET_64BIT) #define RISCV_ATYPE_HI intHI_type_node #define RISCV_ATYPE_SI intSI_type_node #define RISCV_ATYPE_VOID_PTR ptr_type_node +#define RISCV_ATYPE_INT_PTR integer_ptr_type_node /* RISCV_FTYPE_ATYPESN takes N RISCV_FTYPES-like type codes and lists their associated RISCV_ATYPEs. */ diff --git a/gcc/config/riscv/riscv-ftypes.def b/gcc/config/riscv/riscv-ftypes.def index 0d1e4dd061e..3e7d5c69503 100644 --- a/gcc/config/riscv/riscv-ftypes.def +++ b/gcc/config/riscv/riscv-ftypes.def @@ -30,6 +30,7 @@ DEF_RISCV_FTYPE (0, (USI)) DEF_RISCV_FTYPE (0, (VOID)) DEF_RISCV_FTYPE (1, (VOID, USI)) DEF_RISCV_FTYPE (1, (VOID, VOID_PTR)) +DEF_RISCV_FTYPE (1, (USI, VOID_PTR)) DEF_RISCV_FTYPE (1, (USI, USI)) DEF_RISCV_FTYPE (1, (UDI, UDI)) DEF_RISCV_FTYPE (1, (USI, UQI)) diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 70d78151cee..0eac6d44fae 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -411,6 +411,8 @@ Mask(XCVMAC) Var(riscv_xcv_subext) Mask(XCVALU) Var(riscv_xcv_subext) +Mask(XCVELW) Var(riscv_xcv_subext) + TargetVariable int riscv_xthead_subext diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index c8fc4e391b5..b890acccac1 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -21970,6 +21970,14 @@ Generated assembler @code{cv.subuRN} if the uint8_t operand is a constant and in Generated assembler @code{cv.subuRNr} if the it is a register. @end deftypefn +These built-in functions are available for the CORE-V Event Load machine +architecture. For more information on CORE-V ELW builtins, please see +@uref{https://github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md#listing-of-event-load-word-builtins-xcvelw} + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_elw_elw (uint32_t *) +Generated assembler @code{cv.elw} +@end deftypefn + @node RX Built-in Functions @subsection RX Built-in Functions GCC supports some of the RX instructions which cannot be expressed in diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi index c20af31c642..06a6d1776ff 100644 --- a/gcc/doc/sourcebuild.texi +++ b/gcc/doc/sourcebuild.texi @@ -2481,6 +2481,9 @@ Test system has support for the CORE-V MAC extension. @item cv_alu Test system has support for the CORE-V ALU extension. +@item cv_elw +Test system has support for the CORE-V ELW extension. + @end table @subsubsection Other hardware attributes diff --git a/gcc/testsuite/gcc.target/riscv/cv-elw-elw-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-elw-elw-compile-1.c new file mode 100644 index 00000000000..30f951c3f0a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-elw-elw-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_elw } */ +/* { dg-options "-march=rv32i_xcvelw -mabi=ilp32" } */ + +int +foo (void* b) +{ + return __builtin_riscv_cv_elw_elw (b + 8); +} + +/* { dg-final { scan-assembler-times "cv\\.elw\t\[a-z\]\[0-99\],\[0-99\]\\(\[a-z\]\[0-99\]\\)" 1 } } */ diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 024939ee2e7..f388360ae56 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -13085,6 +13085,19 @@ proc check_effective_target_cv_alu { } { } "-march=rv32i_xcvalu" ] } +# Return 1 if the CORE-V ELW extension is available. +proc check_effective_target_cv_elw { } { + if { !([istarget riscv*-*-*]) } { + return 0 + } + return [check_no_compiler_messages cv_elw object { + void foo (void) + { + asm ("cv.elw x0, 0(x0)"); + } + } "-march=rv32i_xcvelw" ] +} + proc check_effective_target_loongarch_sx { } { return [check_no_compiler_messages loongarch_lsx assembly { #if !defined(__loongarch_sx) From patchwork Mon Nov 13 13:35:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mary Bennett X-Patchwork-Id: 1863192 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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Mon, 13 Nov 2023 05:35:46 -0800 (PST) From: Mary Bennett To: gcc-patches@gcc.gnu.org Cc: mary.bennett@embecosm.com Subject: [PATCH v2 2/3] RISC-V: Update XCValu constraints to match other vendors Date: Mon, 13 Nov 2023 13:35:29 +0000 Message-Id: <20231113133530.1727444-3-mary.bennett@embecosm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231113133530.1727444-1-mary.bennett@embecosm.com> References: <20231108110914.2710021-1-mary.bennett@embecosm.com> <20231113133530.1727444-1-mary.bennett@embecosm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org gcc/ChangeLog: * config/riscv/constraints.md: CVP2 -> CV_alu_pow2. * config/riscv/corev.md: Likewise. --- gcc/config/riscv/constraints.md | 15 ++++++++------- gcc/config/riscv/corev.md | 4 ++-- 2 files changed, 10 insertions(+), 9 deletions(-) diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md index 68be4515c04..2711efe68c5 100644 --- a/gcc/config/riscv/constraints.md +++ b/gcc/config/riscv/constraints.md @@ -151,13 +151,6 @@ (define_register_constraint "zmvr" "(TARGET_ZFA || TARGET_XTHEADFMV) ? GR_REGS : NO_REGS" "An integer register for ZFA or XTheadFmv.") -;; CORE-V Constraints -(define_constraint "CVP2" - "Checking for CORE-V ALU clip if ival plus 1 is a power of 2" - (and (match_code "const_int") - (and (match_test "IN_RANGE (ival, 0, 1073741823)") - (match_test "exact_log2 (ival + 1) != -1")))) - ;; Vector constraints. (define_register_constraint "vr" "TARGET_VECTOR ? V_REGS : NO_REGS" @@ -246,3 +239,11 @@ A MEM with a valid address for th.[l|s]*ur* instructions." (and (match_code "mem") (match_test "th_memidx_legitimate_index_p (op, true)"))) + +;; CORE-V Constraints +(define_constraint "CV_alu_pow2" + "@internal + Checking for CORE-V ALU clip if ival plus 1 is a power of 2" + (and (match_code "const_int") + (and (match_test "IN_RANGE (ival, 0, 1073741823)") + (match_test "exact_log2 (ival + 1) != -1")))) diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md index c7a2ba07bcc..92bf0b5d6a6 100644 --- a/gcc/config/riscv/corev.md +++ b/gcc/config/riscv/corev.md @@ -516,7 +516,7 @@ (define_insn "riscv_cv_alu_clip" [(set (match_operand:SI 0 "register_operand" "=r,r") (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") - (match_operand:SI 2 "immediate_register_operand" "CVP2,r")] + (match_operand:SI 2 "immediate_register_operand" "CV_alu_pow2,r")] UNSPEC_CV_ALU_CLIP))] "TARGET_XCVALU && !TARGET_64BIT" @@ -529,7 +529,7 @@ (define_insn "riscv_cv_alu_clipu" [(set (match_operand:SI 0 "register_operand" "=r,r") (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") - (match_operand:SI 2 "immediate_register_operand" "CVP2,r")] + (match_operand:SI 2 "immediate_register_operand" "CV_alu_pow2,r")] UNSPEC_CV_ALU_CLIPU))] "TARGET_XCVALU && !TARGET_64BIT" From patchwork Mon Nov 13 13:35:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mary Bennett X-Patchwork-Id: 1863194 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=embecosm.com header.i=@embecosm.com header.a=rsa-sha256 header.s=google header.b=PHwpH8KF; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; 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d13-20020a056000114d00b003140f47224csm5420493wrx.15.2023.11.13.05.35.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Nov 2023 05:35:47 -0800 (PST) From: Mary Bennett To: gcc-patches@gcc.gnu.org Cc: mary.bennett@embecosm.com Subject: [PATCH v2 3/3] RISC-V: Add support for XCVbi extension in CV32E40P Date: Mon, 13 Nov 2023 13:35:30 +0000 Message-Id: <20231113133530.1727444-4-mary.bennett@embecosm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231113133530.1727444-1-mary.bennett@embecosm.com> References: <20231108110914.2710021-1-mary.bennett@embecosm.com> <20231113133530.1727444-1-mary.bennett@embecosm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md Contributors: Mary Bennett Nandni Jamnadas Pietra Ferreira Charlie Keaney Jessica Mills Craig Blackmore Simon Cook Jeremy Bennett Helene Chelin gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Create XCVbi extension support. * config/riscv/riscv.opt: Likewise. * config/riscv/corev.md: Implement cv_branch pattern for cv.beqimm and cv.bneimm. * config/riscv/riscv.md: Change pattern priority so corev.md patterns run before riscv.md patterns. * config/riscv/constraints.md: Implement constraints cv_bi_s5 - signed 5-bit immediate. * config/riscv/predicates.md: Implement predicate const_int5s_operand - signed 5 bit immediate. * doc/sourcebuild.texi: Add XCVbi documentation. gcc/testsuite/ChangeLog: * gcc.target/riscv/cv-bi-beqimm-compile-1.c: New test. * gcc.target/riscv/cv-bi-beqimm-compile-2.c: New test. * gcc.target/riscv/cv-bi-bneimm-compile-1.c: New test. * gcc.target/riscv/cv-bi-bneimm-compile-2.c: New test. * lib/target-supports.exp: Add proc for XCVbi. --- gcc/common/config/riscv/riscv-common.cc | 2 + gcc/config/riscv/constraints.md | 6 +++ gcc/config/riscv/corev.md | 14 ++++++ gcc/config/riscv/predicates.md | 4 ++ gcc/config/riscv/riscv.md | 11 ++++- gcc/config/riscv/riscv.opt | 2 + gcc/doc/sourcebuild.texi | 3 ++ .../gcc.target/riscv/cv-bi-beqimm-compile-1.c | 17 +++++++ .../gcc.target/riscv/cv-bi-beqimm-compile-2.c | 48 +++++++++++++++++++ .../gcc.target/riscv/cv-bi-bneimm-compile-1.c | 17 +++++++ .../gcc.target/riscv/cv-bi-bneimm-compile-2.c | 48 +++++++++++++++++++ gcc/testsuite/lib/target-supports.exp | 13 +++++ 12 files changed, 184 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 6a1978bd0e4..04631e007f0 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -313,6 +313,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"xcvmac", ISA_SPEC_CLASS_NONE, 1, 0}, {"xcvalu", ISA_SPEC_CLASS_NONE, 1, 0}, {"xcvelw", ISA_SPEC_CLASS_NONE, 1, 0}, + {"xcvbi", ISA_SPEC_CLASS_NONE, 1, 0}, {"xtheadba", ISA_SPEC_CLASS_NONE, 1, 0}, {"xtheadbb", ISA_SPEC_CLASS_NONE, 1, 0}, @@ -1669,6 +1670,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"xcvmac", &gcc_options::x_riscv_xcv_subext, MASK_XCVMAC}, {"xcvalu", &gcc_options::x_riscv_xcv_subext, MASK_XCVALU}, {"xcvelw", &gcc_options::x_riscv_xcv_subext, MASK_XCVELW}, + {"xcvbi", &gcc_options::x_riscv_xcv_subext, MASK_XCVBI}, {"xtheadba", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBA}, {"xtheadbb", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBB}, diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md index 2711efe68c5..718b4bd77df 100644 --- a/gcc/config/riscv/constraints.md +++ b/gcc/config/riscv/constraints.md @@ -247,3 +247,9 @@ (and (match_code "const_int") (and (match_test "IN_RANGE (ival, 0, 1073741823)") (match_test "exact_log2 (ival + 1) != -1")))) + +(define_constraint "CV_bi_sign5" + "@internal + A 5-bit signed immediate for CORE-V Immediate Branch." + (and (match_code "const_int") + (match_test "IN_RANGE (ival, -16, 15)"))) diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md index 92bf0b5d6a6..f6a1f916d7e 100644 --- a/gcc/config/riscv/corev.md +++ b/gcc/config/riscv/corev.md @@ -706,3 +706,17 @@ [(set_attr "type" "load") (set_attr "mode" "SI")]) + +;; XCVBI Builtins +(define_insn "cv_branch" + [(set (pc) + (if_then_else + (match_operator 1 "equality_operator" + [(match_operand:X 2 "register_operand" "r") + (match_operand:X 3 "const_int5s_operand" "CV_bi_sign5")]) + (label_ref (match_operand 0 "" "")) + (pc)))] + "TARGET_XCVBI" + "cv.b%C1imm\t%2,%3,%0" + [(set_attr "type" "branch") + (set_attr "mode" "none")]) diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index a37d035fa61..69a6319c2c8 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -400,6 +400,10 @@ (ior (match_operand 0 "register_operand") (match_code "const_int"))) +(define_predicate "const_int5s_operand" + (and (match_code "const_int") + (match_test "IN_RANGE (INTVAL (op), -16, 15)"))) + ;; Predicates for the V extension. (define_special_predicate "vector_length_operand" (ior (match_operand 0 "pmode_register_operand") diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index ae2217d0907..9a8572e6ef3 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -579,6 +579,16 @@ (define_asm_attributes [(set_attr "type" "multi")]) +;; .............................. +;; +;; Machine Description Patterns +;; +;; .............................. + +;; To encourage the use of CORE-V specific branch instructions, the CORE-V +;; instructions must be defined before the generic RISC-V instructions. +(include "corev.md") + ;; Ghost instructions produce no real code and introduce no hazards. ;; They exist purely to express an effect on dataflow. (define_insn_reservation "ghost" 0 @@ -3632,4 +3642,3 @@ (include "vector.md") (include "zicond.md") (include "zc.md") -(include "corev.md") diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 0eac6d44fae..d06c0f8f416 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -413,6 +413,8 @@ Mask(XCVALU) Var(riscv_xcv_subext) Mask(XCVELW) Var(riscv_xcv_subext) +Mask(XCVBI) Var(riscv_xcv_subext) + TargetVariable int riscv_xthead_subext diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi index 06a6d1776ff..6fee1144238 100644 --- a/gcc/doc/sourcebuild.texi +++ b/gcc/doc/sourcebuild.texi @@ -2484,6 +2484,9 @@ Test system has support for the CORE-V ALU extension. @item cv_elw Test system has support for the CORE-V ELW extension. +@item cv_bi +Test system has support for the CORE-V BI extension. + @end table @subsubsection Other hardware attributes diff --git a/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c new file mode 100644 index 00000000000..5b6ba5b8ae6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_bi } */ +/* { dg-options "-march=rv32i_xcvbi -mabi=ilp32" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } { "" } } */ + +/* __builtin_expect is used to provide the compiler with + branch prediction information and to direct the compiler + to the expected flow through the code. */ + +int +foo1 (int a, int x, int y) +{ + a = __builtin_expect (a, 12); + return a != 10 ? x : y; +} + +/* { dg-final { scan-assembler-times "cv\\.beqimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),10,\(\?\:.L\[0-9\]\)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c b/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c new file mode 100644 index 00000000000..bb2e5843957 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c @@ -0,0 +1,48 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_bi } */ +/* { dg-options "-march=rv32i_xcvbi -mabi=ilp32" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } { "" } } */ + +/* __builtin_expect is used to provide the compiler with + branch prediction information and to direct the compiler + to the expected flow through the code. */ + +int +foo1 (int a, int x, int y) +{ + a = __builtin_expect (a, 10); + return a != -16 ? x : y; +} + +int +foo2 (int a, int x, int y) +{ + a = __builtin_expect (a, 10); + return a != 0 ? x : y; +} + +int +foo3 (int a, int x, int y) +{ + a = __builtin_expect (a, 10); + return a != 15 ? x : y; +} + +int +foo4 (int a, int x, int y) +{ + a = __builtin_expect (a, 10); + return a != -17 ? x : y; +} + +int +foo5 (int a, int x, int y) +{ + a = __builtin_expect (a, 10); + return a != 16 ? x : y; +} + +/* { dg-final { scan-assembler-times "cv\\.beqimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),-16,\(\?\:.L\[0-9\]\)" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.beqimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),0,\(\?\:.L\[0-9\]\)" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.beqimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),15,\(\?\:.L\[0-9\]\)" 1 } } */ +/* { dg-final { scan-assembler-times "beq\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),\(\?\:.L\[0-9\]+\)" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c new file mode 100644 index 00000000000..21eab38a08d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_bi } */ +/* { dg-options "-march=rv32i_xcvbi -mabi=ilp32" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } { "" } } */ + +/* __builtin_expect is used to provide the compiler with + branch prediction information and to direct the compiler + to the expected flow through the code. */ + +int +foo1(int a, int x, int y) +{ + a = __builtin_expect(a, 10); + return a == 10 ? x : y; +} + +/* { dg-final { scan-assembler-times "cv\\.bneimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),10,\(\?\:.L\[0-9\]\)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c b/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c new file mode 100644 index 00000000000..a028f684489 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c @@ -0,0 +1,48 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_bi } */ +/* { dg-options "-march=rv32i_xcvbi -mabi=ilp32" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } { "" } } */ + +/* __builtin_expect is used to provide the compiler with + branch prediction information and to direct the compiler + to the expected flow through the code. */ + +int +foo1(int a, int x, int y) +{ + a = __builtin_expect(a, -16); + return a == -16 ? x : y; +} + +int +foo2(int a, int x, int y) +{ + a = __builtin_expect(a, 0); + return a == 0 ? x : y; +} + +int +foo3(int a, int x, int y) +{ + a = __builtin_expect(a, 15); + return a == 15 ? x : y; +} + +int +foo4(int a, int x, int y) +{ + a = __builtin_expect(a, -17); + return a == -17 ? x : y; +} + +int +foo5(int a, int x, int y) +{ + a = __builtin_expect(a, 16); + return a == 16 ? x : y; +} + +/* { dg-final { scan-assembler-times "cv\\.bneimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),-16,\(\?\:.L\[0-9\]\)" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.bneimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),0,\(\?\:.L\[0-9\]\)" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.bneimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),15,\(\?\:.L\[0-9\]\)" 1 } } */ +/* { dg-final { scan-assembler-times "bne\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),\(\?\:.L\[0-9\]+\)" 2 } } */ diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index f388360ae56..0eae746e848 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -13098,6 +13098,19 @@ proc check_effective_target_cv_elw { } { } "-march=rv32i_xcvelw" ] } +# Return 1 if the CORE-V BI extension is available +proc check_effective_target_cv_bi { } { + if { !([istarget riscv*-*-*]) } { + return 0 + } + return [check_no_compiler_messages cv_bi object { + void foo (void) + { + asm ("cv.beqimm t0, -16, foo"); + } + } "-march=rv32i_xcvbi" ] +} + proc check_effective_target_loongarch_sx { } { return [check_no_compiler_messages loongarch_lsx assembly { #if !defined(__loongarch_sx)