diff mbox series

[01/10] dt-bindings: clock: Add separate clocks for PCIe and USB for Combo PHY

Message ID 20231214062847.2215542-2-quic_ipkumar@quicinc.com
State Changes Requested
Headers show
Series Add PCIe support for Qualcomm IPQ5332 | expand

Checks

Context Check Description
robh/checkpatch success
robh/patch-applied success
robh/dtbs-check warning build log
robh/dt-meta-schema success

Commit Message

Praveenkumar I Dec. 14, 2023, 6:28 a.m. UTC
Qualcomm IPQ5332 has a combo PHY for PCIe and USB. Either one of the
interface (PCIe/USB) can use this combo PHY and the PHY drivers are
different for PCIe and USB. Hence separate the PCIe and USB pipe clock
source from DT, and individual driver node can be used as a clock source
separately in the gcc. Change the dt-bindings accordingly.

Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
---
 .../devicetree/bindings/clock/qcom,ipq5332-gcc.yaml         | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

Comments

Krzysztof Kozlowski Dec. 15, 2023, 8:28 a.m. UTC | #1
On 14/12/2023 07:28, Praveenkumar I wrote:
> Qualcomm IPQ5332 has a combo PHY for PCIe and USB. Either one of the
> interface (PCIe/USB) can use this combo PHY and the PHY drivers are
> different for PCIe and USB. Hence separate the PCIe and USB pipe clock
> source from DT, and individual driver node can be used as a clock source
> separately in the gcc. Change the dt-bindings accordingly.

Adding required clock breaks the ABI and there is no explanation nor
note about it in commit msg

Best regards,
Krzysztof
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml
index 718fe0625424..b22643037119 100644
--- a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml
@@ -28,7 +28,8 @@  properties:
       - description: Sleep clock source
       - description: PCIE 2lane PHY pipe clock source
       - description: PCIE 2lane x1 PHY pipe clock source (For second lane)
-      - description: USB PCIE wrapper pipe clock source
+      - description: PCIE wrapper pipe clock source
+      - description: USB wrapper pipe clock source
 
 required:
   - compatible
@@ -45,7 +46,8 @@  examples:
                <&sleep_clk>,
                <&pcie_2lane_phy_pipe_clk>,
                <&pcie_2lane_phy_pipe_clk_x1>,
-               <&usb_pcie_wrapper_pipe_clk>;
+               <&pcie_wrapper_pipe_clk>,
+               <&usb_wrapper_pipe_clk>;
       #clock-cells = <1>;
       #power-domain-cells = <1>;
       #reset-cells = <1>;