From patchwork Thu Dec 14 06:28:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveenkumar I X-Patchwork-Id: 1875992 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=quicinc.com header.i=@quicinc.com header.a=rsa-sha256 header.s=qcppdkim1 header.b=XHJ8N0TL; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2604:1380:45d1:ec00::1; helo=ny.mirrors.kernel.org; envelope-from=devicetree+bounces-25131-incoming-dt=patchwork.ozlabs.org@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org [IPv6:2604:1380:45d1:ec00::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SrMrv74yjz23nm for ; Thu, 14 Dec 2023 17:29:35 +1100 (AEDT) Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ny.mirrors.kernel.org (Postfix) with ESMTPS id 35BBC1C214CE for ; Thu, 14 Dec 2023 06:29:34 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id CF3B7D296; Thu, 14 Dec 2023 06:29:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="XHJ8N0TL" X-Original-To: devicetree@vger.kernel.org Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BE775B9; Wed, 13 Dec 2023 22:29:25 -0800 (PST) Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BE6O3lW004599; Thu, 14 Dec 2023 06:29:17 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=B8DEEb6RlwnVITJEQM5PUFk9W/h80Pp8iAtLBC8Gsoo=; b=XH J8N0TLetrE18Ii2O6fxXN/KCeL2AsBbIkysZoOElc5gQRWSUFFQ74b+7VSd/wt6z Jnkcv8ScnnYFPRK+MGqgMRDcSqm7a0Ih46cuCZ98fACbFoMD4vzgdhzYvk4laKoG xrF1YPxVbsvHTEDxYtnb+Gnxf4BJs24xGLe417Fidnb5czD+yFb8/XR2wAv6mfjc dNDvl1fm2oEig8GaOyCnSpbARBRxqsNQKFQ4UkGNWFQ0KnBpIWs847JfmcwGQJtR +H5xWz5w1QC4Pk0EkKEA3jvPPWGOfZZ9xe9OZDJ8k+MW58Cg8x1fR9xQLp2I8PAw CTkHal/uveOqx/uc5K6g== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3uyp4xgqef-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 06:29:17 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BE6TGhc016097 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 06:29:16 GMT Received: from hu-ipkumar-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 13 Dec 2023 22:29:08 -0800 From: Praveenkumar I To: , , , , , , , , , , , , , , , , , , , , , CC: , , , Subject: [PATCH 01/10] dt-bindings: clock: Add separate clocks for PCIe and USB for Combo PHY Date: Thu, 14 Dec 2023 11:58:38 +0530 Message-ID: <20231214062847.2215542-2-quic_ipkumar@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231214062847.2215542-1-quic_ipkumar@quicinc.com> References: <20231214062847.2215542-1-quic_ipkumar@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: jtjZ0YZrLMdW4_sZYz0WxqrTZio88GSu X-Proofpoint-ORIG-GUID: jtjZ0YZrLMdW4_sZYz0WxqrTZio88GSu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 mlxlogscore=999 mlxscore=0 priorityscore=1501 malwarescore=0 adultscore=0 spamscore=0 suspectscore=0 phishscore=0 impostorscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312140039 Qualcomm IPQ5332 has a combo PHY for PCIe and USB. Either one of the interface (PCIe/USB) can use this combo PHY and the PHY drivers are different for PCIe and USB. Hence separate the PCIe and USB pipe clock source from DT, and individual driver node can be used as a clock source separately in the gcc. Change the dt-bindings accordingly. Signed-off-by: Praveenkumar I --- .../devicetree/bindings/clock/qcom,ipq5332-gcc.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml index 718fe0625424..b22643037119 100644 --- a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml @@ -28,7 +28,8 @@ properties: - description: Sleep clock source - description: PCIE 2lane PHY pipe clock source - description: PCIE 2lane x1 PHY pipe clock source (For second lane) - - description: USB PCIE wrapper pipe clock source + - description: PCIE wrapper pipe clock source + - description: USB wrapper pipe clock source required: - compatible @@ -45,7 +46,8 @@ examples: <&sleep_clk>, <&pcie_2lane_phy_pipe_clk>, <&pcie_2lane_phy_pipe_clk_x1>, - <&usb_pcie_wrapper_pipe_clk>; + <&pcie_wrapper_pipe_clk>, + <&usb_wrapper_pipe_clk>; #clock-cells = <1>; #power-domain-cells = <1>; #reset-cells = <1>; From patchwork Thu Dec 14 06:28:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveenkumar I X-Patchwork-Id: 1875998 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=quicinc.com header.i=@quicinc.com header.a=rsa-sha256 header.s=qcppdkim1 header.b=WMvSVRkh; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2604:1380:40f1:3f00::1; helo=sy.mirrors.kernel.org; envelope-from=devicetree+bounces-25135-incoming-dt=patchwork.ozlabs.org@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org [IPv6:2604:1380:40f1:3f00::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SrMsV4qRLz23nn for ; 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Thu, 14 Dec 2023 06:29:45 GMT Received: from hu-ipkumar-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 13 Dec 2023 22:29:38 -0800 From: Praveenkumar I To: , , , , , , , , , , , , , , , , , , , , , CC: , , , Subject: [PATCH 05/10] dt-bindings: phy: qcom,uniphy-pcie: Add ipq5332 bindings Date: Thu, 14 Dec 2023 11:58:42 +0530 Message-ID: <20231214062847.2215542-6-quic_ipkumar@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231214062847.2215542-1-quic_ipkumar@quicinc.com> References: <20231214062847.2215542-1-quic_ipkumar@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: FQgD7QvKKfjwdfvvusR2OiHsobtaDXDq X-Proofpoint-ORIG-GUID: FQgD7QvKKfjwdfvvusR2OiHsobtaDXDq X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 mlxscore=0 phishscore=0 clxscore=1015 mlxlogscore=999 priorityscore=1501 lowpriorityscore=0 malwarescore=0 suspectscore=0 bulkscore=0 adultscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312140039 Qualcomm IPQ5332 has single-lane and dual-lane PCIe UNIPHY with Gen 3 support. This UNIPHY is similar to the one found on Qualcomm IPQ5018. Hence add the bindings in qcom,uniphy-pcie. Clocks and resets are different for IPQ5332. Update the bindings to support both IPQ5018 and IPQ5332. Signed-off-by: Praveenkumar I --- This patch depends on the below series which adds PCIe support in Qualcomm IPQ5018 https://lore.kernel.org/all/20231003120846.28626-1-quic_nsekar@quicinc.com/ .../bindings/phy/qcom,uniphy-pcie-28lp.yaml | 65 +++++++++++++++++-- 1 file changed, 58 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/qcom,uniphy-pcie-28lp.yaml b/Documentation/devicetree/bindings/phy/qcom,uniphy-pcie-28lp.yaml index 6b2574f9532e..205eaec2291e 100644 --- a/Documentation/devicetree/bindings/phy/qcom,uniphy-pcie-28lp.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,uniphy-pcie-28lp.yaml @@ -20,19 +20,20 @@ properties: maxItems: 1 clocks: - maxItems: 1 + minItems: 1 + maxItems: 4 clock-names: - items: - - const: pipe_clk + minItems: 1 + maxItems: 4 resets: - maxItems: 2 + minItems: 2 + maxItems: 3 reset-names: - items: - - const: phy - - const: phy_phy + minItems: 2 + maxItems: 3 "#phy-cells": const: 0 @@ -54,6 +55,56 @@ required: - "#clock-cells" - clock-output-names +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq5018-uniphy-pcie-gen2x1 + - qcom,ipq5018-uniphy-pcie-gen2x2 + then: + properties: + clocks: + minItems: 1 + maxItems: 1 + clock-names: + items: + - const: pipe_clk + resets: + minItems: 2 + maxItems: 2 + reset-name: + items: + - const: phy + - const: phy_phy + + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq5332-uniphy-pcie-gen3x1 + - qcom,ipq5332-uniphy-pcie-gen3x2 + then: + properties: + clocks: + minItems: 4 + maxItems: 4 + clock-names: + items: + - const: pipe + - const: lane_m + - const: lane_s + - const: phy_ahb + resets: + minItems: 2 + maxItems: 2 + reset-name: + items: + - const: phy + - const: phy_ahb + additionalProperties: false examples: From patchwork Thu Dec 14 06:28:44 2023 Content-Type: text/plain; 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Thu, 14 Dec 2023 06:30:00 GMT Received: from hu-ipkumar-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 13 Dec 2023 22:29:53 -0800 From: Praveenkumar I To: , , , , , , , , , , , , , , , , , , , , , CC: , , , Subject: [PATCH 07/10] dt-bindings: PCI: qcom: Add IPQ5332 SoC Date: Thu, 14 Dec 2023 11:58:44 +0530 Message-ID: <20231214062847.2215542-8-quic_ipkumar@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231214062847.2215542-1-quic_ipkumar@quicinc.com> References: <20231214062847.2215542-1-quic_ipkumar@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: -Aa4TgoKNCEn7SIisZ3c2z9pAp_XeBZl X-Proofpoint-ORIG-GUID: -Aa4TgoKNCEn7SIisZ3c2z9pAp_XeBZl X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 mlxlogscore=999 mlxscore=0 priorityscore=1501 malwarescore=0 adultscore=0 spamscore=0 suspectscore=0 phishscore=0 impostorscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312140039 Add support for the PCIe controller on the Qualcomm IPQ5332 SoC to the bindings. Signed-off-by: Praveenkumar I --- .../devicetree/bindings/pci/qcom,pcie.yaml | 36 +++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index eadba38171e1..af5e67d2a984 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -21,6 +21,7 @@ properties: - qcom,pcie-apq8064 - qcom,pcie-apq8084 - qcom,pcie-ipq4019 + - qcom,pcie-ipq5332 - qcom,pcie-ipq6018 - qcom,pcie-ipq8064 - qcom,pcie-ipq8064-v2 @@ -170,6 +171,7 @@ allOf: compatible: contains: enum: + - qcom,pcie-ipq5332 - qcom,pcie-ipq6018 - qcom,pcie-ipq8074-gen3 then: @@ -332,6 +334,39 @@ allOf: - const: ahb # AHB reset - const: phy_ahb # PHY AHB reset + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-ipq5332 + then: + properties: + clocks: + minItems: 6 + maxItems: 6 + clock-names: + items: + - const: ahb # AHB clock + - const: aux # Auxiliary clock + - const: axi_m # AXI Master clock + - const: axi_s # AXI Slave clock + - const: axi_bridge # AXI bridge clock + - const: rchng + resets: + minItems: 8 + maxItems: 8 + reset-names: + items: + - const: pipe # PIPE reset + - const: sticky # Core sticky reset + - const: axi_m_sticky # AXI master sticky reset + - const: axi_m # AXI master reset + - const: axi_s_sticky # AXI slave sticky reset + - const: axi_s # AXI slave reset + - const: ahb # AHB reset + - const: aux # AUX reset + - if: properties: compatible: @@ -790,6 +825,7 @@ allOf: enum: - qcom,pcie-apq8064 - qcom,pcie-ipq4019 + - qcom,pcie-ipq5332 - qcom,pcie-ipq8064 - qcom,pcie-ipq8064v2 - qcom,pcie-ipq8074