| Message ID | 20231214062847.2215542-1-quic_ipkumar@quicinc.com |
|---|---|
| Headers | show |
| Series | Add PCIe support for Qualcomm IPQ5332 | expand |
On Thu, 14 Dec 2023 at 08:29, Praveenkumar I <quic_ipkumar@quicinc.com> wrote: > > Qualcomm IPQ5332 has a combo PHY for PCIe and USB. Either one of the > interface (PCIe/USB) can use this combo PHY and the PHY drivers are > different for PCIe and USB. Hence separate the PCIe and USB pipe clock > source from DT, and individual driver node can be used as a clock source > separately in the gcc. Add separate enum for PCIe and USB pipe clock and > change the parent in corresponding structures. > > Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> Please use your full name for the git authorship and or the S-o-B tags. This applies to the whole series. Other than that: Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > drivers/clk/qcom/gcc-ipq5332.c | 7 ++++--- > 1 file changed, 4 insertions(+), 3 deletions(-) > > diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c > index f98591148a97..aa0f616c3b1b 100644 > --- a/drivers/clk/qcom/gcc-ipq5332.c > +++ b/drivers/clk/qcom/gcc-ipq5332.c > @@ -25,7 +25,8 @@ enum { > DT_SLEEP_CLK, > DT_PCIE_2LANE_PHY_PIPE_CLK, > DT_PCIE_2LANE_PHY_PIPE_CLK_X1, > - DT_USB_PCIE_WRAPPER_PIPE_CLK, > + DT_PCIE_WRAPPER_PIPE_CLK, > + DT_USB_WRAPPER_PIPE_CLK, > }; > > enum { > @@ -728,7 +729,7 @@ static struct clk_regmap_phy_mux gcc_pcie3x1_0_pipe_clk_src = { > .hw.init = &(struct clk_init_data) { > .name = "gcc_pcie3x1_0_pipe_clk_src", > .parent_data = &(const struct clk_parent_data) { > - .index = DT_USB_PCIE_WRAPPER_PIPE_CLK, > + .index = DT_PCIE_WRAPPER_PIPE_CLK, > }, > .num_parents = 1, > .ops = &clk_regmap_phy_mux_ops, > @@ -1072,7 +1073,7 @@ static struct clk_regmap_phy_mux gcc_usb0_pipe_clk_src = { > .hw.init = &(struct clk_init_data) { > .name = "gcc_usb0_pipe_clk_src", > .parent_data = &(const struct clk_parent_data) { > - .index = DT_USB_PCIE_WRAPPER_PIPE_CLK, > + .index = DT_USB_WRAPPER_PIPE_CLK, > }, > .num_parents = 1, > .ops = &clk_regmap_phy_mux_ops, > -- > 2.34.1 > >
On Thu, 14 Dec 2023 at 08:30, Praveenkumar I <quic_ipkumar@quicinc.com> wrote: > > Add support for single-lane and dual-lane PCIe UNIPHY found on > Qualcomm IPQ5332 platform. This UNIPHY is similar to the one > present in Qualcomm IPQ5018. > > Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> > --- > This patch depends on the below series which adds PCIe support in > Qualcomm IPQ5018 > https://lore.kernel.org/all/20231003120846.28626-1-quic_nsekar@quicinc.com/ > > .../phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c | 44 +++++++++++++++++++ > 1 file changed, 44 insertions(+) > > diff --git a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c > index 9f9a03faf6fa..aa71b85eb50e 100644 > --- a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c > +++ b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c > @@ -34,6 +34,10 @@ > #define SSCG_CTRL_REG_6 0xb0 > #define PCS_INTERNAL_CONTROL_2 0x2d8 > > +#define PHY_CFG_PLLCFG 0x220 > +#define PHY_CFG_EIOS_DTCT_REG 0x3e4 > +#define PHY_CFG_GEN3_ALIGN_HOLDOFF_TIME 0x3e8 > + > #define PHY_MODE_FIXED 0x1 > > enum qcom_uniphy_pcie_type { > @@ -112,6 +116,21 @@ static const struct uniphy_regs ipq5018_regs[] = { > }, > }; > > +static const struct uniphy_regs ipq5332_regs[] = { > + { > + .offset = PHY_CFG_PLLCFG, > + .val = 0x30, > + }, > + { > + .offset = PHY_CFG_EIOS_DTCT_REG, > + .val = 0x53ef, > + }, > + { > + .offset = PHY_CFG_GEN3_ALIGN_HOLDOFF_TIME, > + .val = 0xCf, > + }, > +}; > + > static const struct uniphy_pcie_data ipq5018_2x2_data = { > .lanes = 2, > .lane_offset = 0x800, > @@ -121,6 +140,23 @@ static const struct uniphy_pcie_data ipq5018_2x2_data = { > .pipe_clk_rate = 125000000, > }; > > +static const struct uniphy_pcie_data ipq5332_x2_data = { > + .lanes = 2, > + .lane_offset = 0x800, > + .phy_type = PHY_TYPE_PCIE_GEN3, > + .init_seq = ipq5332_regs, > + .init_seq_num = ARRAY_SIZE(ipq5332_regs), > + .pipe_clk_rate = 250000000, > +}; > + > +static const struct uniphy_pcie_data ipq5332_x1_data = { > + .lanes = 1, > + .phy_type = PHY_TYPE_PCIE_GEN3, > + .init_seq = ipq5332_regs, > + .init_seq_num = ARRAY_SIZE(ipq5332_regs), > + .pipe_clk_rate = 250000000, > +}; Please keep structs sorted out. > + > static void qcom_uniphy_pcie_init(struct qcom_uniphy_pcie *phy) > { > const struct uniphy_pcie_data *data = phy->data; > @@ -270,6 +306,14 @@ static const struct of_device_id qcom_uniphy_pcie_id_table[] = { > .compatible = "qcom,ipq5018-uniphy-pcie-gen2x2", > .data = &ipq5018_2x2_data, > }, > + { > + .compatible = "qcom,ipq5332-uniphy-pcie-gen3x2", > + .data = &ipq5332_x2_data, > + }, > + { > + .compatible = "qcom,ipq5332-uniphy-pcie-gen3x1", > + .data = &ipq5332_x1_data, The entries here should be sorted out. > + }, > { /* Sentinel */ }, > }; > MODULE_DEVICE_TABLE(of, qcom_uniphy_pcie_id_table); > -- > 2.34.1 > >
On Thu, 14 Dec 2023 at 08:29, Praveenkumar I <quic_ipkumar@quicinc.com> wrote: > > Qualcomm IPQ5332 has the same PCIe UNIPHY PHY with different pipe > clock rate. Add support to define the pipe clock rate in device > data. > > Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> With the name fixed: Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > This patch depends on the below series which adds PCIe support in > Qualcomm IPQ5018 > https://lore.kernel.org/all/20231003120846.28626-1-quic_nsekar@quicinc.com/ > > drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c > index 5ef6ae7276cf..9f9a03faf6fa 100644 > --- a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c > +++ b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c > @@ -54,6 +54,7 @@ struct uniphy_pcie_data { > unsigned int phy_type; > const struct uniphy_regs *init_seq; > unsigned int init_seq_num; > + unsigned int pipe_clk_rate; > }; > > struct qcom_uniphy_pcie { > @@ -117,6 +118,7 @@ static const struct uniphy_pcie_data ipq5018_2x2_data = { > .phy_type = PHY_TYPE_PCIE_GEN2, > .init_seq = ipq5018_regs, > .init_seq_num = ARRAY_SIZE(ipq5018_regs), > + .pipe_clk_rate = 125000000, > }; > > static void qcom_uniphy_pcie_init(struct qcom_uniphy_pcie *phy) > @@ -232,6 +234,7 @@ static int qcom_uniphy_pcie_get_resources(struct platform_device *pdev, > static int phy_pipe_clk_register(struct qcom_uniphy_pcie *phy, > struct device_node *np) > { > + const struct uniphy_pcie_data *data = phy->data; > struct clk_fixed_rate *fixed; > struct clk_init_data init = { }; > int ret; > @@ -247,7 +250,7 @@ static int phy_pipe_clk_register(struct qcom_uniphy_pcie *phy, > return -ENOMEM; > > init.ops = &clk_fixed_rate_ops; > - fixed->fixed_rate = 125000000; > + fixed->fixed_rate = data->pipe_clk_rate; > fixed->hw.init = &init; > > ret = devm_clk_hw_register(phy->dev, &fixed->hw); > -- > 2.34.1 > >
On Thu, 14 Dec 2023 at 08:30, Praveenkumar I <quic_ipkumar@quicinc.com> wrote: > > The Qualcomm IPQ5332 PCIe controller instances are based on > SNPS core 5.90a with Gen3 Single-lane and Dual-lane support. > The Qualcomm IP rev is 1.27.0 and hence using the 1_27_0 ops. > > Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> > --- > This patch depends on the below series which adds PCIe support in > Qualcomm IPQ9574 > https://lore.kernel.org/all/20230519090219.15925-1-quic_devipriy@quicinc.com/ The series did not receive updates since the end of May. Should we expect the next iteration of that series? Otherwise depending on it sounds like a dead end. > > drivers/pci/controller/dwc/pcie-qcom.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index 109df587234e..3d54de1a71df 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -1642,6 +1642,7 @@ static const struct of_device_id qcom_pcie_match[] = { > { .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 }, > { .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 }, > { .compatible = "qcom,pcie-ipq4019", .data = &cfg_2_4_0 }, > + { .compatible = "qcom,pcie-ipq5332", .data = &cfg_1_27_0 }, > { .compatible = "qcom,pcie-ipq6018", .data = &cfg_2_9_0 }, > { .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 }, > { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 }, > -- > 2.34.1 > >
On Thu, 14 Dec 2023 at 08:29, Praveenkumar I <quic_ipkumar@quicinc.com> wrote: > > Add separate entry in clock-controller for USB pipe clock. In my opinion, there is no need to do that separately. Please squash into patch 9. > > Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> > --- > arch/arm64/boot/dts/qcom/ipq5332.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi > index 42e2e48b2bc3..f0d92effb783 100644 > --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi > @@ -213,6 +213,7 @@ gcc: clock-controller@1800000 { > <&sleep_clk>, > <0>, > <0>, > + <0>, > <0>; > }; > > -- > 2.34.1 > >
On 12/14/2023 12:39 PM, Dmitry Baryshkov wrote: > On Thu, 14 Dec 2023 at 08:29, Praveenkumar I <quic_ipkumar@quicinc.com> wrote: >> Qualcomm IPQ5332 has a combo PHY for PCIe and USB. Either one of the >> interface (PCIe/USB) can use this combo PHY and the PHY drivers are >> different for PCIe and USB. Hence separate the PCIe and USB pipe clock >> source from DT, and individual driver node can be used as a clock source >> separately in the gcc. Add separate enum for PCIe and USB pipe clock and >> change the parent in corresponding structures. >> >> Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> > Please use your full name for the git authorship and or the S-o-B > tags. This applies to the whole series. My full name is "Praveenkumar I". In my region, we used to have only the initial letter of surname. -- Thanks, Praveenkumar > Other than that: > > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > >> --- >> drivers/clk/qcom/gcc-ipq5332.c | 7 ++++--- >> 1 file changed, 4 insertions(+), 3 deletions(-) >> >> diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c >> index f98591148a97..aa0f616c3b1b 100644 >> --- a/drivers/clk/qcom/gcc-ipq5332.c >> +++ b/drivers/clk/qcom/gcc-ipq5332.c >> @@ -25,7 +25,8 @@ enum { >> DT_SLEEP_CLK, >> DT_PCIE_2LANE_PHY_PIPE_CLK, >> DT_PCIE_2LANE_PHY_PIPE_CLK_X1, >> - DT_USB_PCIE_WRAPPER_PIPE_CLK, >> + DT_PCIE_WRAPPER_PIPE_CLK, >> + DT_USB_WRAPPER_PIPE_CLK, >> }; >> >> enum { >> @@ -728,7 +729,7 @@ static struct clk_regmap_phy_mux gcc_pcie3x1_0_pipe_clk_src = { >> .hw.init = &(struct clk_init_data) { >> .name = "gcc_pcie3x1_0_pipe_clk_src", >> .parent_data = &(const struct clk_parent_data) { >> - .index = DT_USB_PCIE_WRAPPER_PIPE_CLK, >> + .index = DT_PCIE_WRAPPER_PIPE_CLK, >> }, >> .num_parents = 1, >> .ops = &clk_regmap_phy_mux_ops, >> @@ -1072,7 +1073,7 @@ static struct clk_regmap_phy_mux gcc_usb0_pipe_clk_src = { >> .hw.init = &(struct clk_init_data) { >> .name = "gcc_usb0_pipe_clk_src", >> .parent_data = &(const struct clk_parent_data) { >> - .index = DT_USB_PCIE_WRAPPER_PIPE_CLK, >> + .index = DT_USB_WRAPPER_PIPE_CLK, >> }, >> .num_parents = 1, >> .ops = &clk_regmap_phy_mux_ops, >> -- >> 2.34.1 >> >> >
On 12/14/2023 12:42 PM, Dmitry Baryshkov wrote: > On Thu, 14 Dec 2023 at 08:30, Praveenkumar I <quic_ipkumar@quicinc.com> wrote: >> Add support for single-lane and dual-lane PCIe UNIPHY found on >> Qualcomm IPQ5332 platform. This UNIPHY is similar to the one >> present in Qualcomm IPQ5018. >> >> Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> >> --- >> This patch depends on the below series which adds PCIe support in >> Qualcomm IPQ5018 >> https://lore.kernel.org/all/20231003120846.28626-1-quic_nsekar@quicinc.com/ >> >> .../phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c | 44 +++++++++++++++++++ >> 1 file changed, 44 insertions(+) >> >> diff --git a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c >> index 9f9a03faf6fa..aa71b85eb50e 100644 >> --- a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c >> +++ b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c >> @@ -34,6 +34,10 @@ >> #define SSCG_CTRL_REG_6 0xb0 >> #define PCS_INTERNAL_CONTROL_2 0x2d8 >> >> +#define PHY_CFG_PLLCFG 0x220 >> +#define PHY_CFG_EIOS_DTCT_REG 0x3e4 >> +#define PHY_CFG_GEN3_ALIGN_HOLDOFF_TIME 0x3e8 >> + >> #define PHY_MODE_FIXED 0x1 >> >> enum qcom_uniphy_pcie_type { >> @@ -112,6 +116,21 @@ static const struct uniphy_regs ipq5018_regs[] = { >> }, >> }; >> >> +static const struct uniphy_regs ipq5332_regs[] = { >> + { >> + .offset = PHY_CFG_PLLCFG, >> + .val = 0x30, >> + }, >> + { >> + .offset = PHY_CFG_EIOS_DTCT_REG, >> + .val = 0x53ef, >> + }, >> + { >> + .offset = PHY_CFG_GEN3_ALIGN_HOLDOFF_TIME, >> + .val = 0xCf, >> + }, >> +}; >> + >> static const struct uniphy_pcie_data ipq5018_2x2_data = { >> .lanes = 2, >> .lane_offset = 0x800, >> @@ -121,6 +140,23 @@ static const struct uniphy_pcie_data ipq5018_2x2_data = { >> .pipe_clk_rate = 125000000, >> }; >> >> +static const struct uniphy_pcie_data ipq5332_x2_data = { >> + .lanes = 2, >> + .lane_offset = 0x800, >> + .phy_type = PHY_TYPE_PCIE_GEN3, >> + .init_seq = ipq5332_regs, >> + .init_seq_num = ARRAY_SIZE(ipq5332_regs), >> + .pipe_clk_rate = 250000000, >> +}; >> + >> +static const struct uniphy_pcie_data ipq5332_x1_data = { >> + .lanes = 1, >> + .phy_type = PHY_TYPE_PCIE_GEN3, >> + .init_seq = ipq5332_regs, >> + .init_seq_num = ARRAY_SIZE(ipq5332_regs), >> + .pipe_clk_rate = 250000000, >> +}; > Please keep structs sorted out. sure, will address in next patch set. > >> + >> static void qcom_uniphy_pcie_init(struct qcom_uniphy_pcie *phy) >> { >> const struct uniphy_pcie_data *data = phy->data; >> @@ -270,6 +306,14 @@ static const struct of_device_id qcom_uniphy_pcie_id_table[] = { >> .compatible = "qcom,ipq5018-uniphy-pcie-gen2x2", >> .data = &ipq5018_2x2_data, >> }, >> + { >> + .compatible = "qcom,ipq5332-uniphy-pcie-gen3x2", >> + .data = &ipq5332_x2_data, >> + }, >> + { >> + .compatible = "qcom,ipq5332-uniphy-pcie-gen3x1", >> + .data = &ipq5332_x1_data, > The entries here should be sorted out. will take care. > >> + }, >> { /* Sentinel */ }, >> }; >> MODULE_DEVICE_TABLE(of, qcom_uniphy_pcie_id_table); >> -- >> 2.34.1 >> >> > -- Thanks, Praveenkumar
On 12/14/2023 12:51 PM, Dmitry Baryshkov wrote: > On Thu, 14 Dec 2023 at 08:29, Praveenkumar I <quic_ipkumar@quicinc.com> wrote: >> Add separate entry in clock-controller for USB pipe clock. > In my opinion, there is no need to do that separately. Please squash > into patch 9. Sure will squash this change with patch 9. > >> Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/ipq5332.dtsi | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi >> index 42e2e48b2bc3..f0d92effb783 100644 >> --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi >> +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi >> @@ -213,6 +213,7 @@ gcc: clock-controller@1800000 { >> <&sleep_clk>, >> <0>, >> <0>, >> + <0>, >> <0>; >> }; >> >> -- >> 2.34.1 >> >> > -- Thanks, Praveenkumar
On 14/12/2023 07:28, Praveenkumar I wrote: > Add phy and controller nodes for pcie0_x1 and pcie1_x2. > > Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> > --- > arch/arm64/boot/dts/qcom/ipq5332.dtsi | 189 +++++++++++++++++++++++++- > 1 file changed, 187 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi > index f0d92effb783..367641ab4938 100644 > --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi > @@ -166,6 +166,58 @@ usbphy0: phy@7b000 { > status = "disabled"; > }; > > + pcie0_phy: phy@4b0000{ Nodes look like put in random place. Best regards, Krzysztof
On Fri, 15 Dec 2023 at 07:44, Praveenkumar I <quic_ipkumar@quicinc.com> wrote: > > > > On 12/14/2023 12:39 PM, Dmitry Baryshkov wrote: > > On Thu, 14 Dec 2023 at 08:29, Praveenkumar I <quic_ipkumar@quicinc.com> wrote: > >> Qualcomm IPQ5332 has a combo PHY for PCIe and USB. Either one of the > >> interface (PCIe/USB) can use this combo PHY and the PHY drivers are > >> different for PCIe and USB. Hence separate the PCIe and USB pipe clock > >> source from DT, and individual driver node can be used as a clock source > >> separately in the gcc. Add separate enum for PCIe and USB pipe clock and > >> change the parent in corresponding structures. > >> > >> Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> > > Please use your full name for the git authorship and or the S-o-B > > tags. This applies to the whole series. > My full name is "Praveenkumar I". In my region, we used to have only the > initial letter of surname. Oh, excuse me please then. I saw several of your colleagues using a single letter instead of their surname and I supposed that it's a case for you too.
On Thu, Dec 14, 2023 at 11:58:37AM +0530, Praveenkumar I wrote: > Patch series adds support for enabling the PCIe controller and > UNIPHY found on Qualcomm IPQ5332 platform. PCIe0 is Gen3 X1 and > PCIe1 is Gen3 X2 are added. > > UNIPHY changes depends on > https://lore.kernel.org/all/20231003120846.28626-1-quic_nsekar@quicinc.com/ > PCIe driver change depends on > https://lore.kernel.org/all/20230519090219.15925-1-quic_devipriy@quicinc.com/ > Any plan on this series and the dependencies? - Mani > Praveenkumar I (10): > dt-bindings: clock: Add separate clocks for PCIe and USB for Combo PHY > clk: qcom: ipq5332: Add separate clocks for PCIe and USB for Combo PHY > arm64: dts: qcom: ipq5332: Add separate entry for USB pipe clock > phy: qcom: Add support for Pipe clock rate from device data > dt-bindings: phy: qcom,uniphy-pcie: Add ipq5332 bindings > phy: qcom: ipq5332: Add support for g3x1 and g3x2 PCIe PHYs > dt-bindings: PCI: qcom: Add IPQ5332 SoC > pci: qcom: Add support for IPQ5332 > arm64: dts: qcom: ipq5332: Add PCIe related nodes > arm64: dts: qcom: ipq5332: Enable PCIe phys and controllers > > .../bindings/clock/qcom,ipq5332-gcc.yaml | 6 +- > .../devicetree/bindings/pci/qcom,pcie.yaml | 36 ++++ > .../bindings/phy/qcom,uniphy-pcie-28lp.yaml | 65 +++++- > arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts | 74 +++++++ > arch/arm64/boot/dts/qcom/ipq5332.dtsi | 188 +++++++++++++++++- > drivers/clk/qcom/gcc-ipq5332.c | 7 +- > drivers/pci/controller/dwc/pcie-qcom.c | 1 + > .../phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c | 49 ++++- > 8 files changed, 412 insertions(+), 14 deletions(-) > > -- > 2.34.1 > >