diff mbox series

[5/5] clk: imx: clk-imx8qxp-lpcg: Add some LPCG clocks support for MIPI-LVDS subsystems

Message ID 1605688290-21805-6-git-send-email-victor.liu@nxp.com
State Changes Requested, archived
Headers show
Series Add some clocks support for i.MX8qxp DC0/MIPI-LVDS subsystems | expand

Checks

Context Check Description
robh/checkpatch warning total: 0 errors, 21 warnings, 93 lines checked

Commit Message

Ying Liu Nov. 18, 2020, 8:31 a.m. UTC 
This patch adds some LPCG clocks support for i.MX8qxp MIPI-LVDS subsystems.

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
 drivers/clk/imx/clk-imx8qxp-lpcg.c     | 38 ++++++++++++++++++++++++++++++++++
 drivers/clk/imx/clk-imx8qxp-lpcg.h     |  9 ++++++++
 include/dt-bindings/clock/imx8-clock.h | 26 +++++++++++++++++++++++
 3 files changed, 73 insertions(+)
diff mbox series

Patch

diff --git a/drivers/clk/imx/clk-imx8qxp-lpcg.c b/drivers/clk/imx/clk-imx8qxp-lpcg.c
index 176d426..94c3468 100644
--- a/drivers/clk/imx/clk-imx8qxp-lpcg.c
+++ b/drivers/clk/imx/clk-imx8qxp-lpcg.c
@@ -199,6 +199,42 @@  static const struct imx8qxp_ss_lpcg imx8qxp_ss_lsio = {
 	.num_max = IMX_LSIO_LPCG_CLK_END,
 };
 
+static const struct imx8qxp_lpcg_data imx8qxp_lpcg_mipi_lvds_0[] = {
+	{ IMX_MIPI_LVDS_0_LPCG_LIS_IPG_CLK, "mipi_lvds_0_lpcg_lis_ipg_clk", "mipi_ipg_clk_root", 0, MIPI_LVDS_LIS_LPCG, 16, 0, },
+	{ IMX_MIPI_LVDS_0_LPCG_DI_REGS_IPG_CLK, "mipi_lvds_0_lpcg_di_regs_ipg_clk", "mipi_ipg_clk_root", 0, MIPI_LVDS_DI_REGS_LPCG, 16, 0, },
+	{ IMX_MIPI_LVDS_0_LPCG_GPIO_IPG_CLK, "mipi_lvds_0_lpcg_gpio_ipg_clk", "mipi_ipg_clk_root", 0, MIPI_LVDS_GPIO_LPCG, 16, 0, },
+	{ IMX_MIPI_LVDS_0_LPCG_PWM_IPG_MASTER_CLK, "mipi_lvds_0_lpcg_pwm_ipg_master_clk", "mipi_ipg_clk_root", 0, MIPI_LVDS_PWM_LPCG, 20, 0, },
+	{ IMX_MIPI_LVDS_0_LPCG_PWM_IPG_CLK, "mipi_lvds_0_lpcg_pwm_ipg_clk", "mipi_ipg_clk_root", 0, MIPI_LVDS_PWM_LPCG, 16, 0, },
+	{ IMX_MIPI_LVDS_0_LPCG_PWM_PER_CLK, "mipi_lvds_0_lpcg_pwm_per_clk", "mipi0_pwm0_clk", 0, MIPI_LVDS_PWM_LPCG, 0, 0, },
+	{ IMX_MIPI_LVDS_0_LPCG_PWM_32K_CLK, "mipi_lvds_0_lpcg_pwm_32k_clk", "xtal_32KHz", 0, MIPI_LVDS_PWM_LPCG, 4, 0, },
+	{ IMX_MIPI_LVDS_0_LPCG_I2C0_PER_CLK, "mipi_lvds_0_lpcg_i2c0_per_clk", "mipi0_i2c0_clk", 0, MIPI_LVDS_LPI2C0_LPCG, 0, 0, },
+	{ IMX_MIPI_LVDS_0_LPCG_I2C0_IPG_CLK, "mipi_lvds_0_lpcg_i2c0_ipg_clk", "mipi_ipg_root_clk", 0, MIPI_LVDS_LPI2C0_LPCG, 16, 0, },
+};
+
+static const struct imx8qxp_ss_lpcg imx8qxp_ss_mipi_lvds_0 = {
+	.lpcg = imx8qxp_lpcg_mipi_lvds_0,
+	.num_lpcg = ARRAY_SIZE(imx8qxp_lpcg_mipi_lvds_0),
+	.num_max = IMX_MIPI_LVDS_0_LPCG_CLK_END,
+};
+
+static const struct imx8qxp_lpcg_data imx8qxp_lpcg_mipi_lvds_1[] = {
+	{ IMX_MIPI_LVDS_1_LPCG_LIS_IPG_CLK, "mipi_lvds_1_lpcg_lis_ipg_clk", "mipi_ipg_clk_root", 0, MIPI_LVDS_LIS_LPCG, 16, 0, },
+	{ IMX_MIPI_LVDS_1_LPCG_DI_REGS_IPG_CLK, "mipi_lvds_1_lpcg_di_regs_ipg_clk", "mipi_ipg_clk_root", 0, MIPI_LVDS_DI_REGS_LPCG, 16, 0, },
+	{ IMX_MIPI_LVDS_1_LPCG_GPIO_IPG_CLK, "mipi_lvds_1_lpcg_gpio_ipg_clk", "mipi_ipg_clk_root", 0, MIPI_LVDS_GPIO_LPCG, 16, 0, },
+	{ IMX_MIPI_LVDS_1_LPCG_PWM_IPG_MASTER_CLK, "mipi_lvds_1_lpcg_pwm_ipg_master_clk", "mipi_ipg_clk_root", 0, MIPI_LVDS_PWM_LPCG, 20, 0, },
+	{ IMX_MIPI_LVDS_1_LPCG_PWM_IPG_CLK, "mipi_lvds_1_lpcg_pwm_ipg_clk", "mipi_ipg_clk_root", 0, MIPI_LVDS_PWM_LPCG, 16, 0, },
+	{ IMX_MIPI_LVDS_1_LPCG_PWM_PER_CLK, "mipi_lvds_1_lpcg_pwm_per_clk", "mipi1_pwm0_clk", 0, MIPI_LVDS_PWM_LPCG, 0, 0, },
+	{ IMX_MIPI_LVDS_1_LPCG_PWM_32K_CLK, "mipi_lvds_1_lpcg_pwm_32k_clk", "xtal_32KHz", 0, MIPI_LVDS_PWM_LPCG, 4, 0, },
+	{ IMX_MIPI_LVDS_1_LPCG_I2C0_PER_CLK, "mipi_lvds_1_lpcg_i2c0_per_clk", "mipi1_i2c0_clk", 0, MIPI_LVDS_LPI2C0_LPCG, 0, 0, },
+	{ IMX_MIPI_LVDS_1_LPCG_I2C0_IPG_CLK, "mipi_lvds_1_lpcg_i2c0_ipg_clk", "mipi_ipg_root_clk", 0, MIPI_LVDS_LPI2C0_LPCG, 16, 0, },
+};
+
+static const struct imx8qxp_ss_lpcg imx8qxp_ss_mipi_lvds_1 = {
+	.lpcg = imx8qxp_lpcg_mipi_lvds_1,
+	.num_lpcg = ARRAY_SIZE(imx8qxp_lpcg_mipi_lvds_1),
+	.num_max = IMX_MIPI_LVDS_1_LPCG_CLK_END,
+};
+
 #define IMX_LPCG_MAX_CLKS	8
 
 static struct clk_hw *imx_lpcg_of_clk_src_get(struct of_phandle_args *clkspec,
@@ -397,6 +433,8 @@  static const struct of_device_id imx8qxp_lpcg_match[] = {
 	{ .compatible = "fsl,imx8qxp-lpcg-conn", &imx8qxp_ss_conn, },
 	{ .compatible = "fsl,imx8qxp-lpcg-dc", &imx8qxp_ss_dc, },
 	{ .compatible = "fsl,imx8qxp-lpcg-lsio", &imx8qxp_ss_lsio, },
+	{ .compatible = "fsl,imx8qxp-lpcg-mipi-lvds-0", &imx8qxp_ss_mipi_lvds_0, },
+	{ .compatible = "fsl,imx8qxp-lpcg-mipi-lvds-1", &imx8qxp_ss_mipi_lvds_1, },
 	{ .compatible = "fsl,imx8qxp-lpcg", NULL },
 	{ /* sentinel */ }
 };
diff --git a/drivers/clk/imx/clk-imx8qxp-lpcg.h b/drivers/clk/imx/clk-imx8qxp-lpcg.h
index e1423a9..1505f9b 100644
--- a/drivers/clk/imx/clk-imx8qxp-lpcg.h
+++ b/drivers/clk/imx/clk-imx8qxp-lpcg.h
@@ -119,4 +119,13 @@ 
 #define DC_PRG7_LPCG			0x44
 #define DC_PRG8_LPCG			0x48
 
+/* MIPI-LVDS SS */
+#define MIPI_LVDS_LIS_LPCG		0x00
+#define MIPI_LVDS_DI_REGS_LPCG		0x04
+#define MIPI_LVDS_GPIO_LPCG		0x08
+#define MIPI_LVDS_PWM_LPCG		0x0c
+#define MIPI_LVDS_LPI2C0_LPCG		0x10
+#define MIPI_LVDS_LPI2C1_LPCG		0x14
+#define MIPI_LVDS_MIPI_DSI_LPCG		0x18
+
 #endif /* _IMX8QXP_LPCG_H */
diff --git a/include/dt-bindings/clock/imx8-clock.h b/include/dt-bindings/clock/imx8-clock.h
index c9dd0c6..6922ea9 100644
--- a/include/dt-bindings/clock/imx8-clock.h
+++ b/include/dt-bindings/clock/imx8-clock.h
@@ -325,4 +325,30 @@ 
 
 #define IMX_DC0_LPCG_CLK_END				31
 
+/* MIPI-LVDS0 SS LPCG */
+#define IMX_MIPI_LVDS_0_LPCG_LIS_IPG_CLK		0
+#define IMX_MIPI_LVDS_0_LPCG_DI_REGS_IPG_CLK		1
+#define IMX_MIPI_LVDS_0_LPCG_GPIO_IPG_CLK		2
+#define IMX_MIPI_LVDS_0_LPCG_PWM_IPG_MASTER_CLK		3
+#define IMX_MIPI_LVDS_0_LPCG_PWM_IPG_CLK		4
+#define IMX_MIPI_LVDS_0_LPCG_PWM_PER_CLK		5
+#define IMX_MIPI_LVDS_0_LPCG_PWM_32K_CLK		6
+#define IMX_MIPI_LVDS_0_LPCG_I2C0_PER_CLK		7
+#define IMX_MIPI_LVDS_0_LPCG_I2C0_IPG_CLK		8
+
+#define IMX_MIPI_LVDS_0_LPCG_CLK_END			9
+
+/* MIPI-LVDS1 SS LPCG */
+#define IMX_MIPI_LVDS_1_LPCG_LIS_IPG_CLK		0
+#define IMX_MIPI_LVDS_1_LPCG_DI_REGS_IPG_CLK		1
+#define IMX_MIPI_LVDS_1_LPCG_GPIO_IPG_CLK		2
+#define IMX_MIPI_LVDS_1_LPCG_PWM_IPG_MASTER_CLK		3
+#define IMX_MIPI_LVDS_1_LPCG_PWM_IPG_CLK		4
+#define IMX_MIPI_LVDS_1_LPCG_PWM_PER_CLK		5
+#define IMX_MIPI_LVDS_1_LPCG_PWM_32K_CLK		6
+#define IMX_MIPI_LVDS_1_LPCG_I2C0_PER_CLK		7
+#define IMX_MIPI_LVDS_1_LPCG_I2C0_IPG_CLK		8
+
+#define IMX_MIPI_LVDS_1_LPCG_CLK_END			9
+
 #endif /* __DT_BINDINGS_CLOCK_IMX_H */