| Message ID | 20230816092439.570839-2-jamie.gibbons@microchip.com |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | Update RISC-V Instruction Sets | expand |
On Wed, 16 Aug 2023 10:24:37 +0100 Jamie Gibbons <jamie.gibbons@microchip.com> wrote: > Allow a RISC-V G core to support C and V. Copy custom RVC and RVV > instructions from RISC-V custom core to RISC-V general core. > > v1 -> v2 changes: > - copied RVC and RVV kconfigs to both riscv_g and riscv_custom We don't want to *copy* them. We want to make them available in both cases. Also, the changelog shouldn't go inside the commit log but... > > Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com> > --- ... here, after the "---" line. Thanks! Thomas
Jamie, Thomas, All, On 2023-08-16 14:23 +0200, Thomas Petazzoni via buildroot spake thusly: > On Wed, 16 Aug 2023 10:24:37 +0100 > Jamie Gibbons <jamie.gibbons@microchip.com> wrote: > > > Allow a RISC-V G core to support C and V. Copy custom RVC and RVV > > instructions from RISC-V custom core to RISC-V general core. > > > > v1 -> v2 changes: > > - copied RVC and RVV kconfigs to both riscv_g and riscv_custom > > We don't want to *copy* them. We want to make them available in both > cases. Basically, I think what Thomas expects is something like: diff --git a/arch/Config.in.riscv b/arch/Config.in.riscv index 3dfbb4165f..997f7a631d 100644 --- a/arch/Config.in.riscv +++ b/arch/Config.in.riscv @@ -1,26 +1,5 @@ # RISC-V CPU ISA extensions. -config BR2_RISCV_ISA_RVI - bool - -config BR2_RISCV_ISA_RVM - bool - -config BR2_RISCV_ISA_RVA - bool - -config BR2_RISCV_ISA_RVF - bool - -config BR2_RISCV_ISA_RVD - bool - -config BR2_RISCV_ISA_RVC - bool - -config BR2_RISCV_ISA_RVV - bool - choice prompt "Target Architecture Variant" default BR2_riscv_g @@ -41,38 +20,28 @@ config BR2_riscv_custom endchoice -if BR2_riscv_custom - comment "Instruction Set Extensions" -config BR2_RISCV_ISA_CUSTOM_RVM +config BR2_RISCV_ISA_RVM bool "Integer Multiplication and Division (M)" - select BR2_RISCV_ISA_RVM -config BR2_RISCV_ISA_CUSTOM_RVA +config BR2_RISCV_ISA_RVA bool "Atomic Instructions (A)" - select BR2_RISCV_ISA_RVA -config BR2_RISCV_ISA_CUSTOM_RVF +config BR2_RISCV_ISA_RVF bool "Single-precision Floating-point (F)" - select BR2_RISCV_ISA_RVF -config BR2_RISCV_ISA_CUSTOM_RVD +config BR2_RISCV_ISA_RVD bool "Double-precision Floating-point (D)" depends on BR2_RISCV_ISA_RVF - select BR2_RISCV_ISA_RVD -config BR2_RISCV_ISA_CUSTOM_RVC +config BR2_RISCV_ISA_RVC bool "Compressed Instructions (C)" - select BR2_RISCV_ISA_RVC -config BR2_RISCV_ISA_CUSTOM_RVV +config BR2_RISCV_ISA_RVV bool "Vector Instructions (V)" - select BR2_RISCV_ISA_RVV select BR2_ARCH_NEEDS_GCC_AT_LEAST_12 -endif - choice prompt "Target Architecture Size" default BR2_RISCV_64 Thomas? Regards, Yann E. MORIN. > Also, the changelog shouldn't go inside the commit log but... > > > > > Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com> > > --- > > ... here, after the "---" line. > > Thanks! > > Thomas > -- > Thomas Petazzoni, co-owner and CEO, Bootlin > Embedded Linux and Kernel engineering and training > https://bootlin.com > _______________________________________________ > buildroot mailing list > buildroot@buildroot.org > https://lists.buildroot.org/mailman/listinfo/buildroot
On Wed, 16 Aug 2023 17:04:42 +0200 "Yann E. MORIN" <yann.morin.1998@free.fr> wrote: > Basically, I think what Thomas expects is something like: > > diff --git a/arch/Config.in.riscv b/arch/Config.in.riscv > index 3dfbb4165f..997f7a631d 100644 > --- a/arch/Config.in.riscv > +++ b/arch/Config.in.riscv > @@ -1,26 +1,5 @@ > # RISC-V CPU ISA extensions. > > -config BR2_RISCV_ISA_RVI > - bool > - > -config BR2_RISCV_ISA_RVM > - bool > - > -config BR2_RISCV_ISA_RVA > - bool > - > -config BR2_RISCV_ISA_RVF > - bool > - > -config BR2_RISCV_ISA_RVD > - bool > - > -config BR2_RISCV_ISA_RVC > - bool > - > -config BR2_RISCV_ISA_RVV > - bool > - > choice > prompt "Target Architecture Variant" > default BR2_riscv_g > @@ -41,38 +20,28 @@ config BR2_riscv_custom > > endchoice > > -if BR2_riscv_custom > - > comment "Instruction Set Extensions" > > -config BR2_RISCV_ISA_CUSTOM_RVM > +config BR2_RISCV_ISA_RVM > bool "Integer Multiplication and Division (M)" > - select BR2_RISCV_ISA_RVM > > -config BR2_RISCV_ISA_CUSTOM_RVA > +config BR2_RISCV_ISA_RVA > bool "Atomic Instructions (A)" > - select BR2_RISCV_ISA_RVA > > -config BR2_RISCV_ISA_CUSTOM_RVF > +config BR2_RISCV_ISA_RVF > bool "Single-precision Floating-point (F)" > - select BR2_RISCV_ISA_RVF > > -config BR2_RISCV_ISA_CUSTOM_RVD > +config BR2_RISCV_ISA_RVD > bool "Double-precision Floating-point (D)" > depends on BR2_RISCV_ISA_RVF > - select BR2_RISCV_ISA_RVD > > -config BR2_RISCV_ISA_CUSTOM_RVC > +config BR2_RISCV_ISA_RVC > bool "Compressed Instructions (C)" > - select BR2_RISCV_ISA_RVC > > -config BR2_RISCV_ISA_CUSTOM_RVV > +config BR2_RISCV_ISA_RVV > bool "Vector Instructions (V)" > - select BR2_RISCV_ISA_RVV > select BR2_ARCH_NEEDS_GCC_AT_LEAST_12 > > -endif > - > choice > prompt "Target Architecture Size" > default BR2_RISCV_64 > > Thomas? Not quite, because we want the IMAFD options to remain under the "custom" option. Essentially what happens today is: - RISC-V G implies IMAFD, but there is no way to say I have G + C + V - RISC-V custom allows any combination of IMAFDCV What we want is: - RISC-V G implies IMAFD, but also allows to select C and V - RISC-V custom allows any combination of IMAFDCV So something like this: diff --git a/arch/Config.in.riscv b/arch/Config.in.riscv index 3dfbb4165f..df8499c7a0 100644 --- a/arch/Config.in.riscv +++ b/arch/Config.in.riscv @@ -41,10 +41,10 @@ config BR2_riscv_custom endchoice -if BR2_riscv_custom - comment "Instruction Set Extensions" +if BR2_riscv_custom + config BR2_RISCV_ISA_CUSTOM_RVM bool "Integer Multiplication and Division (M)" select BR2_RISCV_ISA_RVM @@ -62,6 +62,8 @@ config BR2_RISCV_ISA_CUSTOM_RVD depends on BR2_RISCV_ISA_RVF select BR2_RISCV_ISA_RVD +endif + config BR2_RISCV_ISA_CUSTOM_RVC bool "Compressed Instructions (C)" select BR2_RISCV_ISA_RVC @@ -71,8 +73,6 @@ config BR2_RISCV_ISA_CUSTOM_RVV select BR2_RISCV_ISA_RVV select BR2_ARCH_NEEDS_GCC_AT_LEAST_12 -endif - choice prompt "Target Architecture Size" default BR2_RISCV_64 Note that indeed the blind options BR2_RISCV_ISA_RVC and BR2_RISCV_ISA_RVV are no longer very useful, but I guess I would keep them anyway to keep the symmetry with BR2_RISCV_ISA_RV{I,M,A,F,D} blind options. Thoughts? Thomas
Thomas, Jamie, All, On 2023-08-17 09:40 +0200, Thomas Petazzoni via buildroot spake thusly: > On Wed, 16 Aug 2023 17:04:42 +0200 > "Yann E. MORIN" <yann.morin.1998@free.fr> wrote: > > Basically, I think what Thomas expects is something like: [--SNIP--] > > Thomas? > Not quite, because we want the IMAFD options to remain under the > "custom" option. > Essentially what happens today is: > - RISC-V G implies IMAFD, but there is no way to say I have G + C + V > - RISC-V custom allows any combination of IMAFDCV > What we want is: > - RISC-V G implies IMAFD, but also allows to select C and V > - RISC-V custom allows any combination of IMAFDCV > So something like this: With the change Yann@home suggests, it makes it obvious and visible that generic forces IMAFD, without having to guess (or look at generic's help to see what symbols it selects). However, why do we want to expose those extra sets (C, V) to be optional for generic? Isn't that really in fact just defining a custom silicon, which is the reason we have a "custom" choice to begin with? Or do we want to interpret "generic" as "base", e.g. "base that is able to run a Linux system without too much hurdle, anything else less featured will not cope very well at build or runtime, or may restrict the set of packages you may enable; you may enable further extensions" ? Note that G is anyway a superset of IMAFD, as it also contains the Zicsr and Zifencei extensions. In Buildroot, as for the I set, we expect those two extensions to always be available (see arch/arch.mk.riscv@33 and commit d479264b34f2). Regards, Yann E. MORIN.
Hello, On Thu, 17 Aug 2023 10:27:22 +0200 yann.morin@orange.com wrote: > With the change Yann@home suggests, it makes it obvious and visible that > generic forces IMAFD, without having to guess (or look at generic's help > to see what symbols it selects). Ah, I see what you propose. Yes, it also makes sense. > However, why do we want to expose those extra sets (C, V) to be optional > for generic? Isn't that really in fact just defining a custom silicon, > which is the reason we have a "custom" choice to begin with? > > Or do we want to interpret "generic" as "base", e.g. "base that is able > to run a Linux system without too much hurdle, anything else less > featured will not cope very well at build or runtime, or may restrict > the set of packages you may enable; you may enable further extensions" ? That was my idea indeed. To me "G" is a shortcut for IMAFD, but potentially you can have extra extensions as well. > Note that G is anyway a superset of IMAFD, as it also contains the Zicsr > and Zifencei extensions. In Buildroot, as for the I set, we expect those > two extensions to always be available (see arch/arch.mk.riscv@33 and > commit d479264b34f2). Agreed. Thomas
diff --git a/arch/Config.in.riscv b/arch/Config.in.riscv index 3dfbb4165f..48c3236fb6 100644 --- a/arch/Config.in.riscv +++ b/arch/Config.in.riscv @@ -35,6 +35,21 @@ config BR2_riscv_g help General purpose (G) is equivalent to IMAFD. +if BR2_riscv_g + +comment "Instruction Set Extensions" + +config BR2_RISCV_ISA_CUSTOM_RVC + bool "Compressed Instructions (C)" + select BR2_RISCV_ISA_RVC + +config BR2_RISCV_ISA_CUSTOM_RVV + bool "Vector Instructions (V)" + select BR2_RISCV_ISA_RVV + select BR2_ARCH_NEEDS_GCC_AT_LEAST_12 + +endif + config BR2_riscv_custom bool "Custom architecture" select BR2_RISCV_ISA_RVI
Allow a RISC-V G core to support C and V. Copy custom RVC and RVV instructions from RISC-V custom core to RISC-V general core. v1 -> v2 changes: - copied RVC and RVV kconfigs to both riscv_g and riscv_custom Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com> --- arch/Config.in.riscv | 15 +++++++++++++++ 1 file changed, 15 insertions(+)