| Message ID | 20220729000904.1295295-7-joel@jms.id.au |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | powerpc: Fix ppc64le configurations | expand |
On 7/29/22 02:09, Joel Stanley wrote: > The Power10 CPU was released by IBM in 2021. It is a 64-bit CPU > implementing ISA v3.1. It runs in big and little endian modes, and > supports VSX and AltiVec. > > It introduces prefix (8 byte) instructions along side the existing 4 > byte instructions, and new SIMD MMA instructions. > > Power10 is supported as of GCC 10 and Binutils 2.35. > > Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Thanks, C. > --- > arch/Config.in.powerpc | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/arch/Config.in.powerpc b/arch/Config.in.powerpc > index 4c633c338d86..002998d079ee 100644 > --- a/arch/Config.in.powerpc > +++ b/arch/Config.in.powerpc > @@ -155,6 +155,12 @@ config BR2_powerpc_power9 > select BR2_POWERPC_CPU_HAS_ALTIVEC > select BR2_POWERPC_CPU_HAS_VSX > select BR2_ARCH_NEEDS_GCC_AT_LEAST_6 > +config BR2_powerpc_power10 > + bool "power10" > + depends on BR2_ARCH_IS_64 > + select BR2_POWERPC_CPU_HAS_ALTIVEC > + select BR2_POWERPC_CPU_HAS_VSX > + select BR2_ARCH_NEEDS_GCC_AT_LEAST_10 > endchoice > > if BR2_POWERPC_CPU_HAS_SPE > @@ -235,6 +241,7 @@ config BR2_GCC_TARGET_CPU > default "power7" if BR2_powerpc_power7 > default "power8" if BR2_powerpc_power8 > default "power9" if BR2_powerpc_power9 > + default "power10" if BR2_powerpc_power10 > default "powerpc64" if BR2_generic_powerpc64 > default "powerpc" if BR2_generic_powerpc >
diff --git a/arch/Config.in.powerpc b/arch/Config.in.powerpc index 4c633c338d86..002998d079ee 100644 --- a/arch/Config.in.powerpc +++ b/arch/Config.in.powerpc @@ -155,6 +155,12 @@ config BR2_powerpc_power9 select BR2_POWERPC_CPU_HAS_ALTIVEC select BR2_POWERPC_CPU_HAS_VSX select BR2_ARCH_NEEDS_GCC_AT_LEAST_6 +config BR2_powerpc_power10 + bool "power10" + depends on BR2_ARCH_IS_64 + select BR2_POWERPC_CPU_HAS_ALTIVEC + select BR2_POWERPC_CPU_HAS_VSX + select BR2_ARCH_NEEDS_GCC_AT_LEAST_10 endchoice if BR2_POWERPC_CPU_HAS_SPE @@ -235,6 +241,7 @@ config BR2_GCC_TARGET_CPU default "power7" if BR2_powerpc_power7 default "power8" if BR2_powerpc_power8 default "power9" if BR2_powerpc_power9 + default "power10" if BR2_powerpc_power10 default "powerpc64" if BR2_generic_powerpc64 default "powerpc" if BR2_generic_powerpc
The Power10 CPU was released by IBM in 2021. It is a 64-bit CPU implementing ISA v3.1. It runs in big and little endian modes, and supports VSX and AltiVec. It introduces prefix (8 byte) instructions along side the existing 4 byte instructions, and new SIMD MMA instructions. Power10 is supported as of GCC 10 and Binutils 2.35. Signed-off-by: Joel Stanley <joel@jms.id.au> --- arch/Config.in.powerpc | 7 +++++++ 1 file changed, 7 insertions(+)